Skyworks Solutions Inc. SI5350A-B04621-GMR
- Part No.:
- SI5350A-B04621-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- 20-VFQFN Exposed Pad
- Datasheet:
-
SI5350A-B04621-GMR.pdf
- Description:
- IC ANY FREQ ANY OUT XTAL 20QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5350A-B04621-GMR from Skyworks Solutions is a factory-programmed, pin-controlled CMOS clock generator delivering up to 8 independent output frequencies (2.5 kHz–200 MHz) with 0 ppm synthesis error, low period jitter (<70 ps pk-pk), and configurable spread spectrum on any output. It replaces multiple crystals/XOs in audio/video, networking, and embedded systems using a single 25 or 27 MHz crystal reference.
For engineers reviewing the SI5350A-B04621-GMR datasheet, SI5350A-B04621-GMR pinout, SI5350A-B04621-GMR application, or SI5350A-B04621-GMR equivalent, key selection factors include its 20-QFN package with 20 pins, dual-PLL + fractional MultiSynth architecture, independent VDD/VDDO supply rails (1.8/2.5/3.3 V), and support for glitchless frequency switching via FS_0/FS_1 pins.
Technical Context
The SI5350A-B04621-GMR implements two high-frequency PLLs (PLLA and PLLB) feeding eight independent fractional MultiSynth dividers-one per output-enabling simultaneous non-integer-related frequencies. PLLA supports spread spectrum modulation (±0.1% to ±1.5% center-spread, 30–33 kHz rate); PLLB does not.
It uses a fixed 25 or 27 MHz crystal (XA/XB) as sole reference; no external CLKIN capability. Output enable (OEB_0/1/2), power-down (PDN), frequency select (FS_0/FS_1), and spread-spectrum enable (SSEN) are implemented via dedicated programmable control pins P0–P4, with configurable logic thresholds tied to VDD.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count | 8 independent CMOS clock outputs (CLK0–CLK7), each configurable to unique frequencies |
| Frequency range | 2.5 kHz to 200 MHz per output; only two unique frequencies >112.5 MHz simultaneously allowed |
| Period jitter | <70 ps pk-pk typical (all outputs active, worst-case real-world frequency plan) |
| Core supply | 1.71–1.89 V, 2.25–2.75 V, or 3.0–3.6 V - independent of output rail voltage |
| Output supply | VDDOx per output bank (VDDOA–VDDOD) independently set to 1.71–1.89 V, 2.25–2.75 V, or 3.0–3.6 V for level translation |
| Crystal reference | 25 MHz or 27 MHz fundamental-mode AT-cut crystal only (no external clock input) |
| Spread spectrum | Selectable per-output down-spread (–0.1% to –2.5%) or center-spread (±0.1% to ±1.5%), modulated at 30–33 kHz |
Pinout & Package
SI5350A-B04621-GMR is supplied in a 20-pin QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.2 datasheet Section 7.1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GND | Ground reference | Common return for core, outputs, and crystal circuit; requires low-inductance connection to PCB ground plane |
| VDD | Core supply | Supplies PLLs, control logic, and MultiSynths; must be powered before or concurrently with all VDDOx rails |
| VDDOA–VDDOD | Output buffer supplies | Four independent rails powering CLK0–1, CLK2–3, CLK4–5, CLK6–7 banks; enable level-shifting and HCSL-compatible swing at 2.5 V |
| CLK0–CLK7 | CMOS clock outputs | Eight buffered, configurable outputs; each supports invert/non-invert, high/low/Hi-Z disable state, and optional spread spectrum |
| XA / XB | Crystal oscillator inputs | Differential crystal interface; accepts 25 or 27 MHz AT-cut crystal; internal load capacitance selectable (0/6/8/10 pF) |
| P0–P4 | Programmable control pins | P0 = OEB_0 (output enable bank 0), P1 = OEB_1, P2 = OEB_2, P3 = PDN, P4 = SSEN; FS_0/FS_1 mapped internally to CLK0–CLK2 |
Key Features
| Feature | Design Value |
|---|---|
| Factory-programmed configuration | Delivers exact pre-defined frequency plan (no I²C required); eliminates field programming overhead and boot-time delays |
| Glitchless frequency switching | FS_0/FS_1 pins enable zero-cycle interruption when toggling between two pre-configured frequencies on CLK0–CLK2 |
| HCSL-compatible outputs | Configurable 2.5 V VDDOx + external termination enables HCSL-level swing (−0.2 V to 1.0 V) on CLK0–CLK7 pairs |
| Independent VDD/VDDO rails | Allows mixed-voltage system integration: e.g., 1.8 V core with 3.3 V I/O interfaces or 2.5 V HCSL outputs |
| Low-power operation | 25 mA typical core current (8 outputs enabled); 50 µA power-down current with PDN asserted |
Applications
| Audio/Video Processing | Networking Equipment |
|---|---|
Use Scenario: HDMI transmitter, audio codec, and video processor require synchronized clocks at 74.25 MHz, 24.576 MHz, and 48 MHz within a single consumer AV device. IC Role / Device Role / Timing Role: SI5350A-B04621-GMR generates all three frequencies simultaneously from one 27 MHz crystal, replacing discrete oscillators. Use Value: Reduces BOM count, board space, and EMI by eliminating multiple crystal placements and associated layout constraints. | Use Scenario: Ethernet PHY, USB controller, and CPU in a residential gateway need precise, isolated clocks at 125 MHz, 48 MHz, and 33.333 MHz. IC Role / Device Role / Timing Role: SI5350A-B04621-GMR delivers these frequencies with <70 ps period jitter and independent VDDO rails for signal integrity isolation. Use Value: Enables deterministic timing across high-speed interfaces without cross-talk-induced jitter degradation. |
| Embedded Instrumentation | Server/Storage Systems |
Use Scenario: Handheld oscilloscope or spectrum analyzer requires stable, low-jitter clocks for ADC sampling (28.322 MHz), FPGA logic (27 MHz), and display interface (22.5792 MHz). IC Role / Device Role / Timing Role: SI5350A-B04621-GMR synthesizes all three frequencies with 0 ppm error and supports static phase offset for alignment-critical sampling. Use Value: Eliminates calibration drift from aging crystals and ensures repeatable measurement accuracy across temperature. | Use Scenario: PCIe Gen 1-compliant server motherboard needs 100 MHz reference, 125 MHz SerDes clock, and 25 MHz management bus clock. IC Role / Device Role / Timing Role: SI5350A-B04621-GMR provides PCIe Gen 1–qualified outputs with spread spectrum enabled on 100 MHz to meet FCC Class B EMI limits. Use Value: Achieves regulatory compliance without adding ferrites or shielding, reducing system cost and thermal resistance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5350A-B-GM | Blank (unprogrammed) 20-QFN variant requiring ClockBuilder Pro configuration and programming; no factory frequency plan | Suitable for designs needing custom, non-standard frequency sets not covered by preprogrammed variants | Select SI5350A-B-GM only if full frequency flexibility and post-silicon tuning are required; SI5350A-B04621-GMR delivers verified, production-ready timing out-of-box |
| Si5351A-B-GM | I²C-programmable (not pin-controlled); supports external CLKIN in addition to crystal; 8-output 20-QFN but lower max frequency (160 MHz vs. 200 MHz) | Better suited for dynamically reconfigurable systems (e.g., FPGA-based test equipment) where runtime clock changes are needed | Choose Si5351A-B-GM when I²C control and multi-reference support outweigh the need for guaranteed 0 ppm factory calibration and higher-frequency capability |
Compared with SI5350A-B-GM and Si5351A-B-GM, SI5350A-B04621-GMR offers guaranteed 0 ppm frequency accuracy, pin-based control for deterministic startup, and full 200 MHz output capability - critical for fixed-function AV and networking hardware where firmware dependency and frequency margin are unacceptable.
Availability
SI5350A-B04621-GMR is available at Aetrix Electronics and suitable for audio/video processing, networking equipment, and embedded instrumentation requiring stable component supply, guaranteed factory-programmed timing, and long-term lifecycle continuity.
Supply support for SI5350A-B04621-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs.
The SI5350A-B04621-GMR belongs to Skyworks' Si5350 family of factory-programmable clock generators designed for cost-sensitive, high-volume applications requiring replacement of multiple crystals and XOs with a single, flexible, low-jitter timing source.
FAQ
What is the reference clock requirement for SI5350A-B04621-GMR?
The SI5350A-B04621-GMR requires a 25 MHz or 27 MHz fundamental-mode AT-cut crystal connected to XA/XB pins. It does not accept external clock signals - only crystal reference. Internal load capacitance is configurable (0/6/8/10 pF), and ClockBuilder Pro supports fine-tuning with ≤2 pF external capacitors if needed. No other reference sources are supported.
Does SI5350A-B04621-GMR support HCSL output levels?
Yes, SI5350A-B04621-GMR supports HCSL-compatible swing when the corresponding VDDO rail (e.g., VDDOA for CLK0/CLK1) is set to 2.5 V and external 51.1 Ω pull-down resistors are added per output pair. This functionality is validated for 20-QFN and 10-MSOP packages only; the 16-QFN variant does not support HCSL mode.
How many independent frequencies can SI5350A-B04621-GMR generate above 112.5 MHz?
SI5350A-B04621-GMR can simultaneously output exactly two unique frequencies above 112.5 MHz. For example, 125 MHz on CLK0 and 130 MHz on CLK1 is permitted; adding a third distinct frequency >112.5 MHz (e.g., 150 MHz on CLK2) violates the architecture constraint. Duplicate frequencies (e.g., 125 MHz on four outputs) are unrestricted.
What is the power-down current of SI5350A-B04621-GMR?
The power-down current of SI5350A-B04621-GMR is 50 µA maximum when the PDN pin is driven high. In this state, all PLLs, MultiSynths, and output buffers are disabled. Core supply (VDD) and output supplies (VDDOx) remain powered, but no clock activity occurs. Recovery time from power-down is ≤1 ms (TBYP specification).
Can SI5350A-B04621-GMR generate spread spectrum on all eight outputs?
No - spread spectrum is only available on outputs derived from PLLA. Outputs sourced from PLLB (e.g., CLK4–CLK7 in certain configurations) do not support spread spectrum modulation. The SI5350A-B04621-GMR datasheet specifies that spread spectrum is selectable per-output but limited to PLLA-referenced clocks; enabling it on PLLB outputs has no effect.
SI5350A-B04621-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 20-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- -
- PLL:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Divider/Multiplier:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 20-QFN (4x4)
SI5350A-B04621-GMR FAQ
1.How can I place an order for SI5350A-B04621-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5350A-B04621-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5350A-B04621-GMR reliable?
The price and inventory of SI5350A-B04621-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5350A-B04621-GMR is usually 5 days.
3.What payment methods are accepted for SI5350A-B04621-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5350A-B04621-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5350A-B04621-GMR?
SI5350A-B04621-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5350A-B04621-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5350A-B04621-GMR?
For technical support, including SI5350A-B04621-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5350A-B04621-GMR requirements.
6.How does Aetrix verify that SI5350A-B04621-GMR is sourced from the original manufacturer or authorized distributors?
All SI5350A-B04621-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5350A-B04621-GMR meets industry standards.
7.What is the process for return or replacement of SI5350A-B04621-GMR?
All SI5350A-B04621-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5350A-B04621-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5350A-B04621-GMR part is unused and in its original packaging.
Return procedure for SI5350A-B04621-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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