Skyworks Solutions Inc. SI5350A-B04672-GMR
- Part No.:
- SI5350A-B04672-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- 20-VFQFN Exposed Pad
- Datasheet:
-
SI5350A-B04672-GMR.pdf
- Description:
- IC ANY FREQ ANY OUT XTAL 20QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5350A-B04672-GMR from Skyworks Solutions is a factory-programmed, pin-controlled CMOS clock generator with 3 outputs in 10-MSOP package, generating frequencies from 2.5 kHz to 200 MHz per output with 0 ppm synthesis error, <70 ps pk-pk period jitter (typ), and configurable spread spectrum on any output. It replaces multiple crystals/XOs in cost-sensitive audio/video and embedded systems.
For engineers reviewing the SI5350A-B04672-GMR datasheet, SI5350A-B04672-GMR pinout, SI5350A-B04672-GMR application, or SI5350A-B04672-GMR equivalent, key selection criteria include its 3-output 10-MSOP configuration, 25/27 MHz crystal reference requirement, independent VDD/VDDO voltage support (1.8/2.5/3.3 V), glitchless frequency switching via FS pins, and HCSL-compatible swing capability at 2.5 V VDDO.
Technical Context
The SI5350A-B04672-GMR implements a dual-PLL + per-output fractional MultiSynth architecture enabling simultaneous generation of up to three non-integer-related frequencies. Its PLLA-derived outputs support spread spectrum modulation (±0.1% to ±1.5% center-spread or –0.1% to –2.5% down-spread at 30–33 kHz), while PLLB-synchronized outputs do not.
It uses a fixed 25 MHz or 27 MHz AT-cut crystal (XA/XB) as reference, with internal load capacitance options (0/6/8/10 pF) and optional ≤2 pF external capacitors. Output enable (OEB_0/1/2), power-down (PDN), frequency select (FS_0/1), and spread-spectrum enable (SSEN) pins provide direct hardware control without I²C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count | 3 independent CMOS clock outputs (CLK0–CLK2) |
| Frequency range | 2.5 kHz to 200 MHz per output; only two unique frequencies >112.5 MHz allowed simultaneously |
| Period jitter | <70 ps pk-pk (typ), measured across all 3 outputs running at 74.25/24.576/48 MHz |
| Core supply | 1.71–1.89 V, 2.25–2.75 V, or 3.0–3.6 V - supports mixed-voltage system integration |
| Output supply (VDDO) | Independent 1.71–1.89 V, 2.25–2.75 V, or 3.0–3.6 V per output group - enables level translation |
| Reference input | 25 MHz or 27 MHz fundamental-mode AT-cut crystal (XA/XB); no CLKIN support |
| Power consumption | 20–30 mA (typ) with 3 outputs enabled; 50 µA in power-down mode (PDN = high) |
Pinout & Package
SI5350A-B04672-GMR is housed in a 10-pin MSOP package (3.0 × 4.9 mm, 0.65 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5350A-B Rev. 1.2 datasheet Section 7.3 and Figure 4 (10-MSOP block diagram).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD | Core supply | Supplies 1.8/2.5/3.3 V core logic; must be powered before or concurrently with VDDO |
| VDDOA | Output buffer supply A | Powers CLK0, CLK1, CLK2; sets output voltage level and drive strength (50 Ω typ) |
| GND | Ground reference | Analog/digital common return; requires low-inductance connection to thermal pad |
| CLK0 | Output clock 0 | CMOS output; supports F1_0/F2_0 frequency selection via FS_0 when configured |
| CLK1 | Output clock 1 | CMOS output; supports F1_1/F2_1 frequency selection via FS_1 when configured |
| CLK2 | Output clock 2 | CMOS output; supports F1_2/F2_2 frequency selection via FS_0/FS_1 when configured |
| XA | Crytal input A | Connects to one terminal of 25/27 MHz AT-cut crystal; internal load cap configurable |
| XB | Crytal input B | Connects to other crystal terminal; floats if driven by single-ended clock (XA only) |
| OEB_0 | Output enable for CLK0 | Active-low control; configures CLK0 state (high/low/high-Z) when disabled |
| OEB_1 | Output enable for CLK1 | Active-low control; configures CLK1 state (high/low/high-Z) when disabled |
| OEB_2 | Output enable for CLK2 | Active-low control; configures CLK2 state (high/low/high-Z) when disabled |
| PDN | Power-down control | Active-high; places device in 50 µA standby; resets configuration on exit |
| FS_0 | Frequency select 0 | Selects between F1_x/F2_x on CLK0, CLK1, CLK2; enables glitchless switching |
| FS_1 | Frequency select 1 | Secondary select for multi-frequency outputs; used with FS_0 for 2-bit encoding |
| SSEN | Spread spectrum enable | Active-high; globally disables spread spectrum on all PLLA-derived outputs |
Key Features
| Feature | Design Value |
|---|---|
| Factory-programmed frequency plan | Eliminates need for I²C programming hardware; configuration locked at manufacture for production stability |
| Glitchless frequency switching | Hardware-based FS_0/FS_1 control enables zero-cycle interruption during clock rate changes |
| HCSL-compatible swing | Configurable at 2.5 V VDDOA with external 511 Ω/240 Ω termination for differential signaling |
| Independent VDD/VDDO rails | Allows core logic (1.8 V) and output buffers (3.3 V) to operate at different voltages for mixed-signal SoC interfacing |
| Low-power operation | 20–30 mA typical active current and 50 µA power-down current reduce thermal load in space-constrained designs |
| PCIE Gen 1 compliance | Meets jitter and timing requirements for PCIe reference clocks without additional cleanup circuitry |
Applications
| Audio/Video Timing | Embedded System Clocking |
|---|---|
Use Scenario: HDMI transmitter, audio codec, and video processor require synchronized but non-integer-related clocks (e.g., 74.25 MHz, 24.576 MHz, 48 MHz) in set-top boxes or Blu-ray players. IC Role / Device Role / Timing Role: Single-chip clock source replacing three discrete XOs; delivers exact frequencies with 0 ppm error and <70 ps jitter. Use Value: Reduces BOM count, PCB area, and EMI from multiple crystal oscillators while maintaining AV synchronization integrity. |
Use Scenario: Industrial gateway with CPU, Ethernet PHY, and USB controller needing distinct clocks (33.33 MHz, 25 MHz, 48 MHz) from one compact timing source. IC Role / Device Role / Timing Role: Primary clock generator providing isolated, configurable outputs with independent enable/disable and voltage scaling. Use Value: Enables power-gating of unused peripherals via OEB pins and eliminates layout complexity of multiple crystal placements. |
| Residential Networking | Printers & Scanners |
Use Scenario: Wi-Fi router with SoC, RF transceiver, and memory interface requiring low-jitter clocks (125 MHz DDR, 25 MHz MAC, 48 MHz USB). IC Role / Device Role / Timing Role: Factory-configured timing hub delivering PCIe Gen 1-compliant reference and spread-spectrum-capable outputs for EMI reduction. Use Value: Achieves FCC Class B compliance without shielding or ferrites by applying down-spread (–0.1% to –2.5%) selectively on noisy outputs. |
Use Scenario: Multifunction printer using image sensor, motor controller, and display driver - each demanding different clock rates (27 MHz, 28.322 MHz, 22.5792 MHz). IC Role / Device Role / Timing Role: Compact 10-MSOP clock generator replacing legacy crystal+buffer solutions with programmable frequency flexibility. Use Value: Supports field-upgradable timing via FS pin reconfiguration without firmware update or reprogramming. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5350A-B-GT | Blank (unprogrammed) 3-output 10-MSOP variant requiring I²C configuration at startup; no factory frequency plan | Requires microcontroller I²C initialization; unsuitable for systems lacking boot-time firmware control | Select SI5350A-B04672-GMR when deterministic, zero-configuration timing is required at power-on reset. |
| Si5351A-B-GT | I²C-programmable 3-output variant with identical 10-MSOP package but supports CLKIN (not just XTAL) and higher max frequency (250 MHz) | Enables external clock reference and dynamic reconfiguration; adds I²C bus overhead and component count | Choose SI5351A-B-GT only if runtime frequency agility or alternative reference sources (e.g., recovered clock) are mandatory. |
Compared with SI5350A-B-GT and SI5351A-B-GT, SI5350A-B04672-GMR provides guaranteed, immutable timing behavior from power-up with no software dependency, lower system-level jitter due to absence of I²C transaction noise, and reduced bill-of-materials by eliminating pull-up resistors and I²C routing.
Availability
SI5350A-B04672-GMR is available at Aetrix Electronics and suitable for audio/video equipment, residential gateways, and printers/scanners requiring stable component supply, long-term lifecycle assurance, and factory-verified timing performance.
Supply support for SI5350A-B04672-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog technologies.
The Si5350A family is designed for cost-sensitive, space-constrained applications requiring flexible, low-jitter clock generation - specifically targeting crystal/XO replacement in consumer, networking, and industrial embedded systems.
FAQ
What is the reference clock requirement for SI5350A-B04672-GMR?
The SI5350A-B04672-GMR requires a 25 MHz or 27 MHz fundamental-mode AT-cut crystal connected across XA and XB pins. It does not support external clock input (CLKIN) - only crystal reference. Internal load capacitance options (0/6/8/10 pF) and ≤2 pF external capacitors accommodate standard crystal load requirements.
Does SI5350A-B04672-GMR support spread spectrum on all outputs?
SI5350A-B04672-GMR supports spread spectrum only on outputs derived from PLLA. Outputs synchronized to PLLB cannot use spread spectrum. The SSEN pin enables or disables spread spectrum globally across all PLLA outputs. Spread spectrum deviation is selectable from ±0.1% to ±1.5% (center-spread) or –0.1% to –2.5% (down-spread) at 30–33 kHz modulation rate.
Can SI5350A-B04672-GMR generate frequencies above 112.5 MHz?
Yes, SI5350A-B04672-GMR can generate frequencies up to 200 MHz per output, but only two *unique* frequencies above 112.5 MHz may be active simultaneously. For example, 125 MHz on CLK0 and 130 MHz on CLK1 is valid; adding 150 MHz on CLK2 violates the specification. Multiple outputs may replicate the same high-frequency signal (e.g., 125 MHz on all three outputs).
What are the voltage supply requirements for SI5350A-B04672-GMR?
SI5350A-B04672-GMR requires two independent supplies: VDD (core logic) at 1.71–1.89 V, 2.25–2.75 V, or 3.0–3.6 V; and VDDOA (output buffers for CLK0–CLK2) at the same voltage ranges. VDD and VDDOA must be sequenced so VDDOA powers up before or simultaneously with VDD to prevent latch-up.
Is SI5350A-B04672-GMR pin-compatible with other Si5350 variants?
SI5350A-B04672-GMR shares the 10-MSOP package and pinout with all Si5350A-B-GT and Si5350A-Bxxxxx-GT variants. However, functional differences exist: SI5350A-B04672-GMR has factory-programmed frequencies and fixed configuration, whereas blank variants require I²C initialization. Pin compatibility does not imply functional interchangeability without verifying configuration alignment.
SI5350A-B04672-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 20-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- -
- PLL:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Divider/Multiplier:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 20-QFN (4x4)
SI5350A-B04672-GMR FAQ
1.How can I place an order for SI5350A-B04672-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5350A-B04672-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5350A-B04672-GMR reliable?
The price and inventory of SI5350A-B04672-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5350A-B04672-GMR is usually 5 days.
3.What payment methods are accepted for SI5350A-B04672-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5350A-B04672-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5350A-B04672-GMR?
SI5350A-B04672-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5350A-B04672-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5350A-B04672-GMR?
For technical support, including SI5350A-B04672-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5350A-B04672-GMR requirements.
6.How does Aetrix verify that SI5350A-B04672-GMR is sourced from the original manufacturer or authorized distributors?
All SI5350A-B04672-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5350A-B04672-GMR meets industry standards.
7.What is the process for return or replacement of SI5350A-B04672-GMR?
All SI5350A-B04672-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5350A-B04672-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5350A-B04672-GMR part is unused and in its original packaging.
Return procedure for SI5350A-B04672-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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