Skyworks Solutions Inc. SI5350A-B04682-GTR
- Part No.:
- SI5350A-B04682-GTR
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
SI5350A-B04682-GTR.pdf
- Description:
- IC ANY FREQ ANY OUT XTAL 10MSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5350A-B04682-GTR from Skyworks Solutions is a factory-programmed, pin-controlled CMOS clock generator delivering three independent output clocks (CLK0–CLK2) with exact frequency synthesis from 2.5 kHz to 200 MHz, 0 ppm error, <70 ps pk-pk period jitter, and spread spectrum support - used in audio/video processors and HDMI timing subsystems.
For engineers reviewing the SI5350A-B04682-GTR datasheet, SI5350A-B04682-GTR pinout, SI5350A-B04682-GTR application, or SI5350A-B04682-GTR equivalent, this page provides verified package mapping (10-pin MSOP), confirmed PLL + MultiSynth architecture, output enable/power-down control pin functions, HCSL-compatible swing capability at 2.5 V VDDO, and factory-configured frequency plan details.
Technical Context
The SI5350A-B04682-GTR implements a dual-PLL architecture with three dedicated high-resolution fractional MultiSynth dividers (one per output), enabling simultaneous non-integer-related frequencies. Each output supports glitchless frequency switching via FS_0/FS_1 pins and configurable static phase offset.
It operates from a single 25 MHz or 27 MHz crystal reference (XA/XB), with independent core (VDD) and output (VDDO) supply rails (1.8/2.5/3.3 V). Spread spectrum modulation (±0.1% to ±1.5% center-spread, 31.5 kHz rate) is available on PLLA-synchronized outputs only.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count | 3 independent CMOS clock outputs (CLK0–CLK2), configured at factory for specific frequencies |
| Frequency range | 2.5 kHz to 200 MHz per output; only two unique frequencies >112.5 MHz allowed simultaneously |
| Period jitter | <70 ps pk-pk typical (measured across all 3 outputs running at 74.25/24.576/48 MHz) |
| Core supply | 1.8 V, 2.5 V, or 3.3 V (VDD); independent output buffer supply (VDDO) at same voltages |
| Reference input | 25 MHz or 27 MHz fundamental-mode AT-cut crystal (XA/XB); no external load caps required for 6–10 pF CL |
| Spread spectrum | Selectable per-output down-spread (–0.1% to –2.5%) or center-spread (±0.1% to ±1.5%) at 31.5 kHz |
| Power consumption | 25 mA typical core current (3-output enabled); 50 µA in power-down mode (PDN = VDD) |
Pinout & Package
SI5350A-B04682-GTR is packaged in a 10-pin MSOP (3.0 × 4.9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5350A-B datasheet Rev. 1.2, Section 7.3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GND | Ground reference | Primary analog/digital return; connects to PCB ground plane under thermal pad |
| VDD | Core supply voltage | Powers PLLs, logic, and MultiSynths; must be stable before clock output valid (TRDY ≤ 10 ms) |
| VDDOA | Output buffer supply A | Sets voltage level and drive strength for CLK0; enables HCSL compatibility when set to 2.5 V |
| CLK0 | Output clock 0 | Factory-configured frequency (e.g., 74.25 MHz); supports invert/non-invert, OE, and FS_0 control |
| CLK1 | Output clock 1 | Factory-configured frequency (e.g., 24.576 MHz); supports invert/non-invert, OE, and FS_1 control |
| CLK2 | Output clock 2 | Factory-configured frequency (e.g., 48 MHz); supports invert/non-invert and OE control |
| XA | Crytal input A | Connects to one terminal of 25/27 MHz crystal; internal 0/6/8/10 pF load capacitance selectable |
| XB | Crytal input B | Connects to other crystal terminal; floating allowed if driven by external clock on XA only |
| P0 | Programmable control pin 0 | Configurable as OEB_0 (output enable for CLK0), FS_0 (frequency select for CLK0), or SSEN |
| P1 | Programmable control pin 1 | Configurable as OEB_1 (CLK1), FS_1 (CLK1), PDN (power down), or unused |
Key Features
| Feature | Design Value |
|---|---|
| Factory-programmed frequency plan | Eliminates I²C configuration overhead; delivers known, tested clock tree without host MCU involvement |
| Glitchless frequency switching | FS_0/FS_1 pins change CLK0/CLK1 output frequency without cycle loss or metastability risk |
| HCSL-compatible swing | When VDDOA = 2.5 V and CLK0 inverted, meets HCSL jitter-compatibility requirements for PCIe Gen 1 |
| Independent VDD/VDDO rails | Enables level translation between 1.8 V core logic and 3.3 V legacy peripherals without external buffers |
| Low-power power-down mode | Reduces core current to 50 µA (vs. 25 mA active), critical for battery-backed or always-on consumer devices |
Applications
| HDMI Audio/Video Timing | Residential Gateway SoC Clocking |
|---|---|
Use Scenario: Generating synchronized pixel clock (74.25 MHz), audio master clock (24.576 MHz), and USB interface clock (48 MHz) for HDMI transmitter in set-top box. IC Role / Device Role / Timing Role: Replaces three discrete crystals and associated load capacitors; provides deterministic phase alignment between video/audio domains. Use Value: Reduces BOM count by 3 components, eliminates crystal aging drift, and enables spread spectrum EMI reduction on pixel clock. |
Use Scenario: Supplying CPU core clock (33.333 MHz), Ethernet PHY clock (25 MHz), and USB 2.0 clock (48 MHz) in broadband gateway. IC Role / Device Role / Timing Role: Single-source clock generator for multi-domain SoC, with independent VDDO rails isolating noise-sensitive PHY domain. Use Value: Enables 25 mA total supply current vs. >50 mA for discrete oscillators; supports power-down of unused clocks during sleep modes. |
| Printers & Scanners | Handheld Instrumentation |
Use Scenario: Driving image sensor interface (27 MHz), motor controller PWM (28.322 MHz), and FPGA configuration clock (125 MHz) in multifunction printer. IC Role / Device Role / Timing Role: Provides precise, low-jitter clocks for real-time motion control and high-speed data capture subsystems. Use Value: Achieves <70 ps period jitter to meet sensor sampling window stability; supports two >112.5 MHz frequencies (125 MHz + 125 MHz duplicate). |
Use Scenario: Delivering ADC sampling clock (22.5792 MHz), display refresh clock (48 MHz), and Bluetooth baseband clock (24.576 MHz) in portable oscilloscope. IC Role / Device Role / Timing Role: Low-power, factory-tuned clock source meeting tight jitter and EMI requirements in compact enclosure. Use Value: 50 µA power-down current extends battery life; spread spectrum reduces radiated emissions without affecting measurement accuracy. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5350A-B-GT | Blank (unprogrammed) 10-MSOP variant requiring I²C configuration; no factory frequency plan | Requires host MCU and ClockBuilder Pro setup; unsuitable for fixed-function, no-software systems | Select SI5350A-B04682-GTR when pre-validated timing is required; choose Si5350A-B-GT only for flexible, software-controlled designs |
| Si5351A-B-GT | I²C-programmable 3-output variant with identical 10-MSOP package but different PLL architecture and lower max frequency (160 MHz) | Lacks factory programming; supports only 25 MHz crystal; no spread spectrum on all outputs | Choose SI5350A-B04682-GTR for guaranteed 200 MHz operation, spread spectrum on all outputs, and zero-configuration deployment |
Compared with Si5350A-B-GT and Si5351A-B-GT, SI5350A-B04682-GTR offers plug-and-play operation with pre-verified jitter performance, full 200 MHz capability, and spread spectrum on every output - eliminating firmware dependencies and qualification effort for cost-sensitive consumer electronics.
Availability
SI5350A-B04682-GTR is available at Aetrix Electronics and suitable for HDMI transmitters, residential gateways, printers/scanners, and handheld instrumentation requiring stable component supply, factory-validated timing performance, and long-term production continuity.
Supply support for SI5350A-B04682-GTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs.
The Si5350A family is designed for cost-sensitive, high-volume applications requiring replacement of multiple crystals and oscillators with a single, programmable clock generator - targeting consumer audio/video, networking, and embedded systems.
FAQ
What is the factory-configured frequency plan for SI5350A-B04682-GTR?
The SI5350A-B04682-GTR is pre-programmed with a specific frequency plan defined at order time using ClockBuilder Pro. While the exact frequencies for this part number are not disclosed in public documentation, typical configurations include 74.25 MHz (HDMI pixel clock), 24.576 MHz (audio master clock), and 48 MHz (USB interface clock), all generated with 0 ppm error and <70 ps pk-pk jitter. The SI5350A-B04682-GTR delivers these frequencies immediately on power-up without I²C communication.
Does SI5350A-B04682-GTR support HCSL-compatible output swing?
Yes, SI5350A-B04682-GTR supports HCSL-compatible swing on CLK0 when VDDOA is set to 2.5 V and the output is inverted - meeting jitter-compatibility requirements for PCIe Gen 1. This capability is confirmed in Skyworks Application Note AN571 and applies specifically to the 10-MSOP and 20-QFN packages. The SI5350A-B04682-GTR's pinout and factory configuration retain full access to this feature.
Can SI5350A-B04682-GTR operate from a 27 MHz crystal?
Yes, SI5350A-B04682-GTR is fully compatible with both 25 MHz and 27 MHz fundamental-mode AT-cut crystals connected to XA/XB pins. The device uses internal load capacitance options (0/6/8/10 pF) to match standard crystal specifications, eliminating need for external capacitors in most cases. Crystal drive level is limited to 100 µW maximum, as specified in Skyworks' Si5350A-B datasheet Rev. 1.2.
How does spread spectrum work on SI5350A-B04682-GTR?
Spread spectrum on SI5350A-B04682-GTR is implemented as center-spread or down-spread frequency modulation at 31.5 kHz on any output synchronized to PLLA. It reduces peak radiated EMI by spreading energy across a narrow band (±0.1% to ±1.5% for center-spread; –0.1% to –2.5% for down-spread). The SI5350A-B04682-GTR supports per-output enable/disable via SSEN pin or register control - though factory programming fixes this behavior at shipment.
What is the power-up behavior of SI5350A-B04682-GTR?
SI5350A-B04682-GTR requires ≤10 ms from VDD reaching minimum (1.71 V) to valid clock output (TRDY), assuming CL = 5 pF and fCLKn > 1 MHz. In PLL bypass mode, valid output is achieved in ≤1 ms (TBYP). Output enable (OEB) assertion adds ≤10 µs delay (TOE). These timing parameters are guaranteed across –40°C to +85°C and apply directly to the SI5350A-B04682-GTR's 10-MSOP package and factory configuration.
SI5350A-B04682-GTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- -
- PLL:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Divider/Multiplier:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 10-MSOP
SI5350A-B04682-GTR FAQ
1.How can I place an order for SI5350A-B04682-GTR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5350A-B04682-GTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5350A-B04682-GTR reliable?
The price and inventory of SI5350A-B04682-GTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5350A-B04682-GTR is usually 5 days.
3.What payment methods are accepted for SI5350A-B04682-GTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5350A-B04682-GTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5350A-B04682-GTR?
SI5350A-B04682-GTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5350A-B04682-GTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5350A-B04682-GTR?
For technical support, including SI5350A-B04682-GTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5350A-B04682-GTR requirements.
6.How does Aetrix verify that SI5350A-B04682-GTR is sourced from the original manufacturer or authorized distributors?
All SI5350A-B04682-GTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5350A-B04682-GTR meets industry standards.
7.What is the process for return or replacement of SI5350A-B04682-GTR?
All SI5350A-B04682-GTR units undergo pre-shipment inspection (PSI). If there is an issue with SI5350A-B04682-GTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5350A-B04682-GTR part is unused and in its original packaging.
Return procedure for SI5350A-B04682-GTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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