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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5350A-B04817-GTR

Name: SI5350A-B04817-GTR
Brand: Skyworks Solutions Inc.
SKU: SI5350A-B04817-GTR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5350A-B04817-GTR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)

Datasheet:: SI5350A-B04817-GTR.pdf

Description:: IC ANY FREQ ANY OUT XTAL 10MSOP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5350A-B04817-GTR from Skyworks Solutions is a factory-programmed, pin-controlled CMOS clock generator delivering three independent output clocks (CLK0–CLK2) with exact frequency synthesis from 2.5 kHz to 200 MHz, 0 ppm error, <70 ps pk-pk period jitter, and spread spectrum support - deployed in audio/video processors and HDMI timing subsystems.

For engineers reviewing the SI5350A-B04817-GTR datasheet, SI5350A-B04817-GTR pinout, SI5350A-B04817-GTR application, or SI5350A-B04817-GTR equivalent, key selection considerations include its 10-pin MSOP package, 3-output configuration, 25/27 MHz crystal reference requirement, and pin-based control of output enable, frequency select, and spread spectrum enable.

Technical Context

The SI5350A-B04817-GTR implements a dual-PLL + per-output fractional MultiSynth architecture enabling simultaneous non-integer-related frequencies on all three outputs. Its PLLA-synchronized outputs support configurable spread spectrum modulation (±0.1% to ±1.5% center-spread, 30–33 kHz rate), while PLLB-synchronized outputs do not.

It uses a fixed 25 MHz or 27 MHz AT-cut crystal (XA/XB) as reference, with internal load capacitance options (0/6/8/10 pF) and optional external ≤2 pF compensation. Output drive strength is fixed at 50 Ω impedance, supporting CMOS-level swing and HCSL-compatible operation when VDDO = 2.5 V.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	3 independent CMOS clock outputs (CLK0–CLK2), each programmable to any frequency from 2.5 kHz to 200 MHz
Frequency accuracy	0 ppm error - eliminates need for trimming or calibration in production
Period jitter	<70 ps pk-pk (typ), measured across 10k cycles with default high-drive 50 Ω output impedance
Crystal reference	25 MHz or 27 MHz fixed-frequency AT-cut crystal only - no CLKIN or voltage-controlled input support
Supply flexibility	Independent core (VDD: 1.71–3.6 V) and output (VDDO: 1.71–3.6 V) rails - enables level translation between logic domains
Spread spectrum	Selectable per-output down-spread (–0.1% to –2.5%) or center-spread (±0.1% to ±1.5%), modulated at 30–33 kHz
Power consumption	20–30 mA core current (typ) with 3 outputs enabled; 50 µA in power-down mode (PDN = high)

Pinout & Package

SI5350A-B04817-GTR is packaged in a 10-pin MSOP (3.0 × 4.9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Rev. 1.2 datasheet Section 7.3 and Figure 4 (10-MSOP block diagram).

Pin/Terminal	Circuit Role	Design Meaning
VDD	Core supply rail	Accepts 1.71–3.6 V; powers PLLs, logic, and MultiSynths - must be powered before or simultaneously with VDDO
VDDOA, VDDOB, VDDOC	Output buffer supply rails	Independent 1.71–3.6 V supplies per output group - enable level translation (e.g., 1.8 V core / 3.3 V outputs)
CLK0, CLK1, CLK2	CMOS clock outputs	Configurable frequencies up to 200 MHz; each supports invert/non-invert, high/low/Hi-Z disable state, and optional F1/F2 dual-frequency selection
XA, XB	Crystal oscillator inputs	Differential connection for 25 or 27 MHz AT-cut crystal; internal load caps (0/6/8/10 pF) configurable via ClockBuilder Pro
P0, P1, P2	Programmable control pins	P0 = OEB_0 (CLK0 enable), P1 = OEB_1 (CLK1 enable), P2 = OEB_2 (CLK2 enable); active-low, CMOS-compatible
P3	Power-down control	PDN: active-high shutdown - reduces current to 50 µA; device resumes within 2–10 ms after deassertion
P4	Spread spectrum enable	SSEN: active-high global disable for spread spectrum on all PLLA-synchronized outputs

Key Features

Feature	Design Value
Glitchless frequency switching	Enables real-time clock rate changes (e.g., video format switching) without output interruption or metastability
Rise/fall time control	1–1.5 ns (20–80%, CL = 5 pF) - ensures clean edge integrity for high-speed interfaces like HDMI and USB
Static phase offset support	Allows deterministic inter-output phase alignment - critical for multi-lane serializers/deserializers and JESD204B timing
PSRR optimization	Eliminates need for external LDOs or ferrite beads - simplifies power delivery network design
HCSL compatibility	When VDDO = 2.5 V and INV function enabled, outputs meet HCSL swing requirements for PCIe Gen1 and SATA

Applications

Audio/Video Timing	HDMI Source Timing
Use Scenario: Synchronizing audio sample rates (24.576 MHz), video pixel clocks (74.25 MHz), and system clocks (48 MHz) in set-top boxes and Blu-ray players. IC Role / Device Role / Timing Role: Replaces three discrete crystals or XOs with a single programmable source, reducing BOM count and board space. Use Value: Eliminates frequency tolerance stacking and enables precise inter-clock phase relationships required for lip-sync accuracy.	Use Scenario: Generating TMDS clock (74.25 MHz), audio clock (22.5792 MHz), and auxiliary clocks (28.322 MHz, 48 MHz) for HDMI transmitter ICs in residential gateways. IC Role / Device Role / Timing Role: Provides multiple non-integer-related frequencies from one reference crystal, avoiding complex clock tree design. Use Value: Reduces EMI through per-output spread spectrum - critical for passing FCC Part 15 Class B emissions limits.
USB Audio Interface	Embedded Video Processor
Use Scenario: Delivering 48 MHz USB SOF clock, 24.576 MHz I2S master clock, and 27 MHz video interface clock in portable DAC/headphone amplifiers. IC Role / Device Role / Timing Role: Supplies synchronized low-jitter clocks to USB PHY, audio codec, and display controller from shared 27 MHz crystal. Use Value: Achieves <70 ps period jitter - meets USB Audio Class 2.0 jitter requirements for 24-bit/192 kHz playback.	Use Scenario: Clocking video processing ASICs requiring 33.333 MHz CPU clock, 74.25 MHz pixel clock, and 125 MHz DDR interface clock in projectors and digital signage. IC Role / Device Role / Timing Role: Generates all required clocks from single 25 MHz crystal - avoids clock domain crossing issues and skew. Use Value: Supports static phase offset configuration to align DDR write strobes with data eye - improves memory timing margin.

Audio/Video Timing

HDMI Source Timing

Use Scenario: Synchronizing audio sample rates (24.576 MHz), video pixel clocks (74.25 MHz), and system clocks (48 MHz) in set-top boxes and Blu-ray players.

IC Role / Device Role / Timing Role: Replaces three discrete crystals or XOs with a single programmable source, reducing BOM count and board space.

Use Value: Eliminates frequency tolerance stacking and enables precise inter-clock phase relationships required for lip-sync accuracy.

Use Scenario: Generating TMDS clock (74.25 MHz), audio clock (22.5792 MHz), and auxiliary clocks (28.322 MHz, 48 MHz) for HDMI transmitter ICs in residential gateways.

IC Role / Device Role / Timing Role: Provides multiple non-integer-related frequencies from one reference crystal, avoiding complex clock tree design.

Use Value: Reduces EMI through per-output spread spectrum - critical for passing FCC Part 15 Class B emissions limits.

USB Audio Interface

Embedded Video Processor

Use Scenario: Delivering 48 MHz USB SOF clock, 24.576 MHz I2S master clock, and 27 MHz video interface clock in portable DAC/headphone amplifiers.

IC Role / Device Role / Timing Role: Supplies synchronized low-jitter clocks to USB PHY, audio codec, and display controller from shared 27 MHz crystal.

Use Value: Achieves <70 ps period jitter - meets USB Audio Class 2.0 jitter requirements for 24-bit/192 kHz playback.

Use Scenario: Clocking video processing ASICs requiring 33.333 MHz CPU clock, 74.25 MHz pixel clock, and 125 MHz DDR interface clock in projectors and digital signage.

IC Role / Device Role / Timing Role: Generates all required clocks from single 25 MHz crystal - avoids clock domain crossing issues and skew.

Use Value: Supports static phase offset configuration to align DDR write strobes with data eye - improves memory timing margin.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5350A-B-GT	Blank (unprogrammed) version requiring ClockBuilder Pro configuration and programming; same 10-MSOP package and 3-output capability	Requires post-manufacturing programming step - unsuitable for turnkey production without programming infrastructure	Select SI5350A-B04817-GTR for drop-in use; choose Si5350A-B-GT only if custom frequency plans are needed beyond factory configuration
Si5351A-B-GT	I²C-configurable (not pin-controlled); supports 3 outputs but requires external EEPROM or host MCU for initialization; higher typical jitter (95 ps pk-pk)	Needs firmware integration and I²C bus resources - adds design complexity vs. pin-strapped simplicity of SI5350A-B04817-GTR	Prefer SI5350A-B04817-GTR for cost-sensitive, firmware-light designs; Si5351A-B-GT suits systems with existing I²C infrastructure and dynamic reconfiguration needs

Compared with Si5350A-B-GT and Si5351A-B-GT, SI5350A-B04817-GTR delivers immediate plug-and-play operation with guaranteed factory-set frequencies, lower jitter, and zero firmware dependency - making it optimal for high-volume consumer audio/video timing where predictability and BOM reduction are critical.

Availability

SI5350A-B04817-GTR is available at Aetrix Electronics and suitable for HDMI timing subsystems, USB audio interfaces, embedded video processors, and residential gateway platforms requiring stable component supply and guaranteed factory-programmed performance.

Supply support for SI5350A-B04817-GTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5350A-B product line delivers factory-programmable, pin-controlled clock generators targeting cost-sensitive consumer electronics that replace multiple crystals and oscillators with a single configurable device.

FAQ

What reference crystal frequency does the SI5350A-B04817-GTR require?

The SI5350A-B04817-GTR requires a fixed 25 MHz or 27 MHz AT-cut crystal connected to XA/XB pins. It does not accept external clock inputs or voltage-controlled references. Internal load capacitance (0/6/8/10 pF) is configurable via ClockBuilder Pro, and external ≤2 pF compensation is supported for crystals requiring 12 pF load.

Does the SI5350A-B04817-GTR support HCSL-compatible outputs?

Yes, the SI5350A-B04817-GTR supports HCSL-compatible swing when VDDO is set to 2.5 V and the INV function is enabled on one clock of a pair - but only in 10-MSOP and 20-QFN packages. The 10-MSOP package (used by SI5350A-B04817-GTR) supports this mode for CLK0/CLK1 or CLK1/CLK2 pairs with appropriate external termination (511 Ω pull-up, 240 Ω AC-coupled to ground).

How many unique high-frequency outputs can the SI5350A-B04817-GTR generate above 112.5 MHz?

The SI5350A-B04817-GTR can simultaneously output no more than two unique frequencies above 112.5 MHz. For example, 125 MHz on CLK0 and 130 MHz on CLK1 is allowed, but adding 150 MHz on CLK2 violates the specification. Multiple copies of the same high-frequency signal (e.g., 125 MHz on all three outputs) are permitted.

What is the power-down behavior of the SI5350A-B04817-GTR?

When PDN (pin P3) is driven high, the SI5350A-B04817-GTR enters full power-down mode, drawing ≤50 µA. All outputs cease, PLLs stop, and internal state is lost. Upon PDN deassertion (low), the device powers up in ≤10 ms (typical 2 ms), restoring factory-programmed frequencies without host intervention.

Can the SI5350A-B04817-GTR generate different frequencies on CLK0 and CLK1 using pin control?

Yes - the SI5350A-B04817-GTR supports dual-frequency per-output (F1_x/F2_x) on CLK0 and CLK1 via FS_0 and FS_1 pins. However, SI5350A-B04817-GTR is a factory-programmed variant: its specific F1/F2 values and FS pin mapping are fixed per order. The part number suffix "B04817" indicates its preconfigured frequency plan, which must be verified in Skyworks' ClockBuilder Pro-generated configuration report.

SI5350A-B04817-GTR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 10-MSOP

SI5350A-B04817-GTR FAQ

1.How can I place an order for SI5350A-B04817-GTR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5350A-B04817-GTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5350A-B04817-GTR reliable?

The price and inventory of SI5350A-B04817-GTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5350A-B04817-GTR is usually 5 days.

3.What payment methods are accepted for SI5350A-B04817-GTR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5350A-B04817-GTR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5350A-B04817-GTR?

SI5350A-B04817-GTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5350A-B04817-GTR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5350A-B04817-GTR?

For technical support, including SI5350A-B04817-GTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5350A-B04817-GTR requirements.

6.How does Aetrix verify that SI5350A-B04817-GTR is sourced from the original manufacturer or authorized distributors?

All SI5350A-B04817-GTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5350A-B04817-GTR meets industry standards.

7.What is the process for return or replacement of SI5350A-B04817-GTR?

All SI5350A-B04817-GTR units undergo pre-shipment inspection (PSI). If there is an issue with SI5350A-B04817-GTR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5350A-B04817-GTR part is unused and in its original packaging.

Return procedure for SI5350A-B04817-GTR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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