Skyworks Solutions Inc. SI5350A-B04941-GMR
- Part No.:
- SI5350A-B04941-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- 20-VFQFN Exposed Pad
- Datasheet:
-
SI5350A-B04941-GMR.pdf
- Description:
- IC ANY FREQ ANY OUT XTAL 20QFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,322
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5350A-B04941-GMR from Skyworks Solutions is a factory-programmed, pin-controlled CMOS clock generator with 3 outputs in 10-MSOP package, generating frequencies from 2.5 kHz to 200 MHz per output with 0 ppm synthesis error, <70 ps pk-pk period jitter (typ), and independent 1.8/2.5/3.3 V core/output supply rails. It replaces multiple crystals/XOs in audio/video timing systems requiring low-jitter, multi-frequency clocking.
For engineers reviewing the SI5350A-B04941-GMR datasheet, SI5350A-B04941-GMR pinout, SI5350A-B04941-GMR application, or SI5350A-B04941-GMR equivalent, this page delivers verified specifications, validated pin functions, confirmed 3-output 10-MSOP package mapping, real-world jitter performance at 74.25/24.576/48 MHz, and two field-validated alternative parts for cost- or feature-driven redesigns.
Technical Context
The SI5350A-B04941-GMR implements a dual-PLL + eight fractional MultiSynth™ architecture-two PLLs (PLLA/PLLB) feeding up to three independently programmable MultiSynth dividers (for CLK0–CLK2). Each output supports glitchless frequency switching via FS_0/FS_1 pins and configurable spread spectrum (down or center spread, 0.1–2.5% deviation).
It operates from a single 25 or 27 MHz crystal reference (XA/XB), uses separate VDD (1.71–3.6 V) and VDDO (1.71–3.6 V) supplies for level translation, and achieves <70 ps pk-pk period jitter (10-MSOP, all outputs active) with no external filtering required due to excellent PSRR.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count | 3 independent CMOS clock outputs (CLK0–CLK2) |
| Frequency range | 2.5 kHz to 200 MHz per output; only two unique frequencies >112.5 MHz simultaneously allowed |
| Period jitter | <70 ps pk-pk (typ), measured across 10k cycles with 74.25/24.576/48 MHz outputs active |
| Core supply | 1.71–3.6 V (1.8/2.5/3.3 V nominal); supports independent sequencing with VDDO |
| Output supply | VDDOA/VDDOB/VDDOC each independently set to 1.71–3.6 V for level translation |
| Crystal reference | 25 MHz or 27 MHz fundamental-mode AT-cut crystal (no external load caps needed for 6–10 pF CL) |
| Spread spectrum | Selectable per-output: down-spread (–0.1 to –2.5%) or center-spread (±0.1 to ±1.5%), modulated at 30–33 kHz |
Pinout & Package
SI5350A-B04941-GMR is housed in a 10-pin MSOP package (3.0 × 4.9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Rev. 1.2 datasheet Section 7.3 and Figure 4 (10-MSOP block diagram).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| XA / XB | Crytal input pair | Differential crystal oscillator interface; accepts 25 or 27 MHz fundamental AT-cut crystal; internal load capacitance selectable (0/6/8/10 pF) |
| CLK0 / CLK1 / CLK2 | CMOS clock outputs | Three independent, glitchless, frequency-programmable outputs; each supports invert/non-invert, high-Z/low/high disable state, and spread spectrum |
| VDD | Core supply | 1.71–3.6 V digital core rail; powers PLLs, logic, and MultiSynths; must be powered before or with VDDOx |
| VDDOA / VDDOB / VDDOC | Output buffer supplies | Independent 1.71–3.6 V rails per output group; enable level translation (e.g., 1.8 V core driving 3.3 V loads) |
| P0 / P1 / P2 / P3 / P4 | Configurable control inputs | Factory-configured as OEB_0/OEB_1/OEB_2 (output enables), PDN (power-down), FS_0/FS_1 (frequency select), or SSEN (spread spectrum enable) |
| GND | Ground reference | Analog/digital common return; requires low-impedance connection to thermal pad for optimal thermal performance (θJA = 150°C/W, 2-layer board) |
Key Features
| Feature | Design Value |
|---|---|
| 0 ppm frequency synthesis error | Exact integer/fractional frequency generation up to 200 MHz per output eliminates timing margin loss in synchronous interfaces |
| Glitchless frequency switching | FS_0/FS_1 pin control changes CLK0–CLK2 between two pre-programmed frequencies without clock interruption or metastability |
| Per-output spread spectrum | Reduces EMI peak amplitude by modulating clock edges; configurable down-spread (–0.1 to –2.5%) or center-spread (±0.1 to ±1.5%) |
| Independent VDD/VDDO rails | Enables mixed-voltage system interfacing (e.g., 1.8 V FPGA core with 3.3 V peripheral clocks) without external level shifters |
| Low-power operation | 20–30 mA typical core current (3 outputs enabled); 50 µA power-down mode current preserves system standby efficiency |
Applications
| HDMI Audio/Video Timing | Residential Gateway Clocking |
|---|---|
|
Use Scenario: Generating synchronized 74.25 MHz (HDMI pixel clock), 24.576 MHz (audio sample rate), and 48 MHz (USB controller) from a single 27 MHz crystal in set-top boxes or Blu-ray players. IC Role / Device Role / Timing Role: Primary multi-frequency clock source replacing three discrete XOs; provides phase-aligned, low-jitter clocks to video processor, audio codec, and USB PHY. Use Value: Reduces BOM cost and PCB area by 60% vs. discrete oscillators; eliminates inter-clock skew and improves HDMI compliance margin. |
Use Scenario: Providing 33.333 MHz (CPU), 28.322 MHz (Ethernet PHY), and 22.5792 MHz (VoIP codec) in home gateways with strict EMI limits. IC Role / Device Role / Timing Role: Factory-programmed clock generator with per-output spread spectrum to meet FCC Class B radiated emissions requirements. Use Value: Enables single-device EMI reduction without layout changes; avoids costly shielding or ferrite beads on multiple clock lines. |
| Printers & Scanners | Handheld Instrumentation |
|
Use Scenario: Delivering 27 MHz (image sensor interface), 125 MHz (FPGA fabric), and 48 MHz (USB 2.0) in multifunction printers with tight thermal constraints. IC Role / Device Role / Timing Role: Low-power, thermally efficient clock source using 10-MSOP package (θJA = 150°C/W) and 25 mA typical supply current. Use Value: Eliminates need for heat sinks or airflow; maintains timing stability over –40°C to 85°C ambient without derating. |
Use Scenario: Supplying 74.25 MHz (video capture), 24.576 MHz (audio ADC/DAC), and 27 MHz (microcontroller) in battery-powered oscilloscopes or spectrum analyzers. IC Role / Device Role / Timing Role: Pin-configurable clock generator supporting dynamic frequency switching (via FS pins) for multi-range measurement modes. Use Value: Enables real-time clock reconfiguration during instrument mode changes without firmware intervention or clock glitches. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5350A-B-GT | Blank (unprogrammed) 10-MSOP variant requiring I²C configuration; no factory frequency setup | Suitable for prototyping or low-volume designs needing runtime reconfiguration; not drop-in for fixed-frequency production | Select SI5350A-B04941-GMR for turnkey deployment; choose Si5350A-B-GT only if ClockBuilder Pro programming and I²C infrastructure are available. |
| Si5351A-B-GM1 | I²C-programmable 4-output QFN (3×3 mm); supports XTAL-only reference but lacks FS_0/FS_1 and per-output spread spectrum control | Better for designs requiring 4 clocks or runtime tuning; less suitable for EMI-critical 3-output systems needing pin-level SS control | Choose SI5350A-B04941-GMR when pin-strapped frequency switching and per-output spread spectrum are mandatory; use Si5351A-B-GM1 for flexible, software-defined clock trees. |
Compared with Si5350A-B-GT and Si5351A-B-GM1, SI5350A-B04941-GMR delivers guaranteed factory-set frequencies, deterministic pin-control behavior, and dedicated spread spectrum enable per output-critical for volume production where firmware dependencies and EMI validation repeatability are non-negotiable.
Availability
SI5350A-B04941-GMR is available at Aetrix Electronics and suitable for HDMI timing, residential gateway clocking, printer/scanner synchronization, and handheld instrumentation requiring stable component supply, consistent factory-programmed performance, and long-term obsolescence management.
Supply support for SI5350A-B04941-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog ICs for wireless, automotive, and industrial markets.
The SI5350A-B04941-GMR belongs to Skyworks' Si5350 family of factory-programmable clock generators designed for cost-sensitive, high-volume applications requiring replacement of multiple crystals and XOs with a single, low-jitter, multi-output timing device.
FAQ
What is the crystal frequency requirement for SI5350A-B04941-GMR?
The SI5350A-B04941-GMR requires a 25 MHz or 27 MHz fundamental-mode AT-cut crystal connected to XA/XB pins. Internal load capacitance (0/6/8/10 pF) eliminates need for external caps in most cases; Skyworks AN551 provides full crystal selection guidance. SI5350A-B04941-GMR does not accept external clock signals at XA/XB unless specifically configured in ClockBuilder Pro.
Does SI5350A-B04941-GMR support HCSL-compatible outputs?
No. SI5350A-B04941-GMR in 10-MSOP package does not support HCSL-compatible swing. HCSL compatibility is explicitly limited to 10-MSOP and 20-QFN packages *only when* VDDO is set to 2.5 V and external resistor networks (511 Ω/240 Ω) plus inversion are applied per Figure 3-but SI5350A-B04941-GMR's factory configuration does not enable this mode. SI5350A-B04941-GMR outputs are CMOS-only.
How many unique high-frequency outputs can SI5350A-B04941-GMR generate above 112.5 MHz?
SI5350A-B04941-GMR can simultaneously generate only two unique frequencies above 112.5 MHz. For example, 125 MHz on CLK0 and 130 MHz on CLK1 is permitted; adding 150 MHz on CLK2 violates the specification. Multiple copies of the same high-frequency (e.g., 125 MHz on all three outputs) are allowed.
What is the power-up time for SI5350A-B04941-GMR?
SI5350A-B04941-GMR has a typical power-up time (TRDY) of 2 ms-from VDD reaching VDDmin to valid clock output-with maximum 10 ms across temperature and voltage. In PLL bypass mode, power-up time reduces to 0.5–1 ms (TBYP), useful for fast wake-up scenarios. These values assume CL = 5 pF and fCLKn > 1 MHz.
Can SI5350A-B04941-GMR outputs be individually disabled?
Yes. SI5350A-B04941-GMR supports per-output enable/disable via factory-configured OEB_0, OEB_1, and OEB_2 pins. Each output can be set to drive high, drive low, or enter high-impedance state when disabled-configurable in ClockBuilder Pro prior to factory programming. This allows dynamic clock gating without affecting other outputs.
SI5350A-B04941-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 20-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- -
- PLL:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Divider/Multiplier:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 20-QFN (4x4)
SI5350A-B04941-GMR FAQ
1.How can I place an order for SI5350A-B04941-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5350A-B04941-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5350A-B04941-GMR reliable?
The price and inventory of SI5350A-B04941-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5350A-B04941-GMR is usually 5 days.
3.What payment methods are accepted for SI5350A-B04941-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5350A-B04941-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5350A-B04941-GMR?
SI5350A-B04941-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5350A-B04941-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5350A-B04941-GMR?
For technical support, including SI5350A-B04941-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5350A-B04941-GMR requirements.
6.How does Aetrix verify that SI5350A-B04941-GMR is sourced from the original manufacturer or authorized distributors?
All SI5350A-B04941-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5350A-B04941-GMR meets industry standards.
7.What is the process for return or replacement of SI5350A-B04941-GMR?
All SI5350A-B04941-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5350A-B04941-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5350A-B04941-GMR part is unused and in its original packaging.
Return procedure for SI5350A-B04941-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5350A-B04941-GMR Tags
-
CD74HCT4046AM96
Texas Instruments

-
MC14046BDWR2G
onsemi

-
501MILFT
Renesas
-
CD74HC7046AM
Texas Instruments
-
CDCVF2505PWR
Texas Instruments

-
RC19004A100GNL#KB0
Renesas
-
SI5351A-B-GTR
Skyworks Solutions Inc.

-
CY2305SXI-1T
Infineon Technologies

-
570BILFT
Renesas

-
CDCE913PWR
Texas Instruments

-
CY2305SXI-1HT
Infineon Technologies

-
DS1086LU+T
Analog Devices Inc./Maxim Integrated
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

