Skyworks Solutions Inc. SI5350A-B05288-GM

Overview

SI5350A-B05288-GM from Skyworks Solutions is a factory-programmed, pin-controlled CMOS clock generator with 8 independent outputs, synthesizing frequencies from 2.5 kHz to 200 MHz with 0 ppm error using a 25/27 MHz crystal reference. It features dual PLL + fractional MultiSynth architecture, <70 ps pk-pk period jitter (typ), and configurable spread spectrum on any output - deployed in audio/video processors, HDMI interfaces, and Ethernet PHY timing systems.

For engineers reviewing the SI5350A-B05288-GM datasheet, SI5350A-B05288-GM pinout, SI5350A-B05288-GM application, or SI5350A-B05288-GM equivalent, key selection criteria include its 20-QFN package with 20-pin layout, 8-output capability, per-output frequency select (FS_0/FS_1), HCSL-compatible swing support at 2.5 V VDDO, and factory-programmed configuration eliminating I²C initialization.

Technical Context

The SI5350A-B05288-GM implements two high-frequency PLLs (PLLA and PLLB) feeding eight independent fractional MultiSynth dividers - enabling simultaneous non-integer-related output frequencies up to 200 MHz. Each output supports glitchless frequency switching via FS_0/FS_1 control pins, and spread spectrum modulation (±0.1% to ±1.5%, 30–33 kHz) is available only on PLLA-synchronized outputs.

It operates from a single 25 MHz or 27 MHz AT-cut crystal (XA/XB), with internal load capacitance options (0/6/8/10 pF) and separate core (VDD) and output (VDDOx) supply rails (1.8/2.5/3.3 V). Power-down (PDN), output enable (OEB_0/1/2), and spread spectrum enable (SSEN) are implemented as dedicated programmable control pins (P0–P4).

Key Specifications

Pinout & Package

SI5350A-B05288-GM is packaged in a 20-pin QFN (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.2 datasheet Section 7.1.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5350A-B-GM and Si5351A-B-GM, SI5350A-B05288-GM delivers immediate, deterministic timing on power-up without software dependency - critical for HDMI, USB, and Ethernet applications where clock stability must be guaranteed within 2 ms of VDD ramp.

Availability

SI5350A-B05288-GM is available at Aetrix Electronics and suitable for HDMI transceivers, Ethernet PHYs, USB 2.0 host controllers, and multi-standard video processors requiring stable component supply and guaranteed factory-programmed timing behavior.

Supply support for SI5350A-B05288-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs.

The Si5350A family is designed for cost-sensitive, high-volume applications requiring replacement of multiple crystals and oscillators with a single, programmable, low-jitter clock source - targeting consumer audio/video, networking, and embedded computing markets.

FAQ

What is the reference clock requirement for SI5350A-B05288-GM?

The SI5350A-B05288-GM requires a 25 MHz or 27 MHz fundamental-mode AT-cut crystal connected to XA/XB pins. It does not accept external clock signals unless modified per AN551; the device uses internal load capacitors (0/6/8/10 pF) and supports optional external caps ≤2 pF for crystal matching. No oscillator module or CLKIN signal is used in this factory-programmed variant.

Does SI5350A-B05288-GM support HCSL output levels?

Yes, SI5350A-B05288-GM supports HCSL-compatible swing when VDDOx is set to 2.5 V and external resistors (R1 = 511 Ω, R2 = 240 Ω) are applied per output pair (e.g., CLK0/CLK1 with VDDOA = 2.5 V). This functionality is validated only in the 20-QFN and 10-MSOP packages, and requires one output to be inverted to form a differential pair.

How many frequencies can SI5350A-B05288-GM generate above 112.5 MHz simultaneously?

SI5350A-B05288-GM can output only two unique frequencies above 112.5 MHz at the same time - for example, 125 MHz on CLK0 and 130 MHz on CLK1. Multiple copies of the same high-frequency signal (e.g., 125 MHz on CLK0–CLK3) are permitted, but three distinct frequencies >112.5 MHz (e.g., 125/130/150 MHz) violate the device's synthesis resource limits.

Is SI5350A-B05288-GM pin-compatible with other Si5350A variants in 20-QFN?

Yes, SI5350A-B05288-GM shares identical 20-pin QFN (4×4 mm) mechanical and electrical pinout with all Si5350A-B-GM and Si5350A-Bxxxxx-GM variants. Pin functions (XA/XB, CLK0–CLK7, VDDOA–VDDOD, P0–P4, FS_0/FS_1) are fully consistent across the 20-QFN family, enabling drop-in replacement where configuration matches.

What is the power-up timing behavior of SI5350A-B05288-GM?

SI5350A-B05288-GM achieves valid output clocks within 2 ms (typ) after VDD reaches minimum operating voltage (TRDY), assuming CL = 5 pF and fCLKn > 1 MHz. In PLL bypass mode, valid output is achieved within 0.5 ms (typ). These values are guaranteed across –40°C to +85°C ambient and apply to all 8 outputs simultaneously.