Skyworks Solutions Inc. SI5350A-B05587-GTR

Overview

SI5350A-B05587-GTR from Skyworks Solutions is a factory-programmed, pin-controlled CMOS clock generator delivering three independent output clocks (CLK0–CLK2) in a 10-pin MSOP package. It synthesizes frequencies from 2.5 kHz to 200 MHz with 0 ppm error using a 25 or 27 MHz crystal reference, supports glitchless dual-frequency switching via FS_0/FS_1 pins, and features configurable spread spectrum on each output for EMI reduction - deployed in HDMI audio/video timing and residential gateway clocking.

For engineers reviewing the SI5350A-B05587-GTR datasheet, SI5350A-B05587-GTR pinout, SI5350A-B05587-GTR application, or SI5350A-B05587-GTR equivalent, key selection criteria include its fixed 3-output MSOP configuration, factory-programmed frequency plan, PLL+MultiSynth architecture, 70 ps pk-pk period jitter (all outputs active), and support for HCSL-compatible swing at 2.5 V VDDO with external termination.

Technical Context

The SI5350A-B05587-GTR implements a dual-PLL architecture (PLLA and PLLB) with three dedicated high-resolution fractional MultiSynth™ dividers - one per output - enabling simultaneous synthesis of non-integer-related frequencies up to 200 MHz. Each output supports independent spread spectrum modulation (down-spread: –0.1% to –2.5%; center-spread: ±0.1% to ±1.5%) at 30–33 kHz rate, selectable per output via internal configuration.

It operates from a single 25 or 27 MHz fundamental-mode AT-cut crystal (XA/XB), with programmable internal load capacitance (0/6/8/10 pF). Core and output supplies are independently configurable at 1.8 V, 2.5 V, or 3.3 V, and power-down (PDN), output enable (OEB_0/1/2), and frequency select (FS_0/FS_1) pins provide direct hardware control without I²C interface.

Key Specifications

Pinout & Package

SI5350A-B05587-GTR is housed in a 10-pin MSOP package (3.0 × 4.9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.2 datasheet Section 7.3 and Figure 4 (10-MSOP block diagram).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with SI5350A-B-GT and Si5351A-B-GT, SI5350A-B05587-GTR delivers deterministic factory-set timing, hardware-based frequency agility, and HCSL compatibility - making it optimal for cost-sensitive, production-ready designs where I²C overhead and layout flexibility are secondary to guaranteed performance and reduced qualification effort.

Availability

SI5350A-B05587-GTR is available at Aetrix Electronics and suitable for HDMI audio/video timing, residential gateway clocking, printers & scanners, and handheld instrumentation requiring stable component supply, guaranteed factory-programmed frequency plans, and long-term obsolescence management.

Supply support for SI5350A-B05587-GTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog technologies.

The Si5350A family is designed for cost-sensitive, high-volume applications requiring flexible, low-jitter clock generation - specifically targeting replacement of multiple crystals and XOs in consumer, networking, and embedded systems where board space and BOM count are critical constraints.

FAQ

What reference crystal frequency does the SI5350A-B05587-GTR require?

The SI5350A-B05587-GTR requires either a 25 MHz or 27 MHz fundamental-mode AT-cut crystal connected to XA and XB pins. It does not support external clock input (CLKIN) or voltage-controlled crystal oscillator (VCXO) references - only crystal-based operation per the SI5350A datasheet Rev. 1.2. The internal load capacitance is programmable (0/6/8/10 pF) to match common crystal specifications.

Does the SI5350A-B05587-GTR support HCSL-compatible outputs?

Yes, the SI5350A-B05587-GTR supports HCSL-compatible swing on any output when its corresponding VDDO rail (e.g., VDDOA for CLK0) is set to 2.5 V and terminated with the external resistor network shown in Figure 3 of the datasheet (511 Ω pull-down + 240 Ω series). This capability is confirmed for the 10-MSOP package and enables direct interface with PCIe Gen 1 receivers and legacy differential clock loads.

Can the SI5350A-B05587-GTR generate more than two frequencies above 112.5 MHz simultaneously?

No. The SI5350A-B05587-GTR - like all Si5350A variants - permits only two unique frequencies above 112.5 MHz across all outputs at once. For example, 125 MHz on CLK0 and 130 MHz on CLK1 is allowed, but adding 150 MHz on CLK2 violates the specification. Multiple copies of the same high-frequency (e.g., 125 MHz on CLK0 and CLK1) are permitted without restriction.

How is frequency selection implemented on the SI5350A-B05587-GTR?

Frequency selection on the SI5350A-B05587-GTR uses dedicated hardware pins FS_0 (P0) and FS_1 (P1) to toggle between two pre-programmed frequencies (F1_x and F2_x) on each output (CLK0–CLK2). This enables glitchless, hardware-triggered switching - for instance, changing HDMI pixel clock from 74.25 MHz to 74.25/1.001 MHz during video format transitions - without firmware intervention or I²C bus activity.

What is the maximum period jitter specification for the SI5350A-B05587-GTR?

The SI5350A-B05587-GTR has a typical period jitter of <70 ps pk-pk when all three outputs are active, measured under worst-case real-world frequency plan conditions (74.25/24.576/48 MHz outputs, 10-MSOP package). This value is specified at default high-drive strength (50 Ω output impedance) and applies across the full operating temperature range (–40°C to +85°C) per Table 7 of the Rev. 1.2 datasheet.