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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5350A-B05598-GTR

Name: SI5350A-B05598-GTR
Brand: Skyworks Solutions Inc.
SKU: SI5350A-B05598-GTR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5350A-B05598-GTR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)

Datasheet:: SI5350A-B05598-GTR.pdf

Description:: IC ANY FREQ ANY OUT XTAL 10MSOP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5350A-B05598-GTR from Skyworks Solutions is a factory-programmed, pin-controlled CMOS clock generator with 3 outputs in 10-MSOP package, generating frequencies from 2.5 kHz to 200 MHz with 0 ppm synthesis error, <70 ps pk-pk period jitter, and spread spectrum support on any output - used for HDMI video timing, USB controller clocks, and Ethernet PHY synchronization in audio/video equipment.

For engineers reviewing the SI5350A-B05598-GTR datasheet, SI5350A-B05598-GTR pinout, SI5350A-B05598-GTR application, or SI5350A-B05598-GTR equivalent, key selection factors include its fixed 25/27 MHz crystal reference, independent VDD/VDDO voltage scaling (1.8/2.5/3.3 V), glitchless frequency switching via FS pins, HCSL-compatible swing at 2.5 V VDDO, and factory-programmed configuration eliminating I²C initialization.

Technical Context

The SI5350A-B05598-GTR implements a dual-PLL + eight fractional MultiSynth architecture, where PLLA drives all outputs and PLLB supports static phase offset and auxiliary synthesis paths. Its 3-output variant uses MultiSynth 0–2 with configurable F1_x/F2_x dual-frequency capability per output, controlled by FS_0/FS_1 pins.

It operates from a single 25 MHz or 27 MHz fundamental-mode AT-cut crystal (XA/XB), with internal load capacitance options (0/6/8/10 pF) and no external crystal capacitors required for standard 6–12 pF crystals. Power sequencing mandates VDDOx powered before or concurrently with VDD.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	3 independent CMOS clock outputs (CLK0–CLK2)
Frequency range	2.5 kHz to 200 MHz per output; only two unique frequencies >112.5 MHz simultaneously allowed
Period jitter	<70 ps pk-pk (typ), measured across 10k cycles at default 50 Ω drive strength
Core supply	1.71–1.89 V / 2.25–2.75 V / 3.0–3.6 V - supports mixed-voltage system integration
Output supply (VDDO)	Independent 1.71–1.89 V / 2.25–2.75 V / 3.0–3.6 V per output group - enables level translation to downstream logic
Crystal reference	25 MHz or 27 MHz fixed-frequency AT-cut crystal only - no CLKIN support
Spread spectrum	Selectable per-output down-spread (–0.1% to –2.5%) or center-spread (±0.1% to ±1.5%) at 30–33 kHz modulation rate

Pinout & Package

SI5350A-B05598-GTR is packaged in a 10-pin MSOP (3.0 × 4.9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Rev. 1.2 datasheet Section 7.3 and Figure 4 (10-MSOP block diagram).

Pin/Terminal	Circuit Role	Design Meaning
GND	Ground reference	Common return for core and output supplies; must be low-impedance connection to PCB ground plane
VDD	Core supply input	Supplies PLLs, control logic, and MultiSynths; requires local 100 nF + 10 µF decoupling
VDDOA	Output buffer supply for CLK0	Sets logic level and drive strength for CLK0; independent of VDD and other VDDO pins
VDDOB	Output buffer supply for CLK1	Enables level translation for CLK1 - e.g., 2.5 V for HCSL compatibility when paired with CLK0
VDDOC	Output buffer supply for CLK2	Allows mixed-voltage clock distribution - e.g., 1.8 V for low-power MCU interface, 3.3 V for legacy peripherals
CLK0	Primary clock output	CMOS output with programmable rise/fall time; supports invert/non-invert and high-Z disable state
CLK1	Secondary clock output	Glitchless frequency switching available when linked to FS_0/FS_1; configurable duty cycle (45–55% @ <160 MHz)
CLK2	Tertiary clock output	Supports spread spectrum modulation if sourced from PLLA; can be powered down individually to reduce current
XA	Crytal input (high-side)	Accepts 25/27 MHz fundamental-mode crystal; internal 6/8/10 pF load capacitance selectable via ClockBuilder Pro
XB	Crytal input (low-side)	Differential crystal node; must be floated if driving XA with single-ended clock signal

Key Features

Feature	Design Value
Factory-programmed configuration	Eliminates I²C bus, firmware, and configuration EEPROM - reduces BOM and boot-time latency
Dual-frequency per output (F1_x/F2_x)	Enables dynamic clock rate switching (e.g., 74.25 MHz ↔ 74.25/1.001 MHz) without software intervention
HCSL-compatible swing at 2.5 V VDDO	Meets JEDEC HCSL jitter specs when CLK0/CLK1 share 2.5 V VDDO and one is inverted - supports PCIe Gen1 interfaces
Independent VDDO per output group	Permits simultaneous interfacing to 1.8 V FPGAs, 2.5 V SerDes, and 3.3 V microcontrollers without level shifters
Low power consumption	20–30 mA typical core current with 3 outputs active - optimized for cost-sensitive consumer electronics

Applications

HDMI Video Timing	USB Controller Clocking
Use Scenario: Generating precise pixel clocks (74.25 MHz) and audio sample clocks (24.576 MHz) for HDMI transmitters in set-top boxes and Blu-ray players. IC Role / Device Role / Timing Role: Primary clock source replacing multiple XOs; provides synchronized, low-jitter clocks with static phase offset control. Use Value: Eliminates board space and EMI from discrete oscillators while meeting HDMI CTS jitter limits (<150 ps pk-pk).	Use Scenario: Supplying 48 MHz USB 2.0 reference clock and 12 MHz suspend/resume clock to USB host controllers in residential gateways. IC Role / Device Role / Timing Role: Single-device clock source for USB PHY layer timing, supporting both active and low-power states. Use Value: Reduces component count vs. dual-XO solution; spread spectrum on 48 MHz output lowers radiated emissions during FCC testing.
Ethernet PHY Synchronization	Audio/Video Processor Interface
Use Scenario: Delivering 25 MHz or 28.322 MHz reference clocks to Ethernet PHYs (e.g., Broadcom BCM54210) in networking switches and routers. IC Role / Device Role / Timing Role: Low-jitter clock generator with robust PSRR, immune to power rail noise from adjacent switch-mode regulators. Use Value: Meets IEEE 802.3 jitter tolerance (≤1.5 UI) without external filtering; 70 ps pk-pk jitter ensures clean eye diagrams.	Use Scenario: Providing 33.333 MHz CPU clock, 27 MHz video processor clock, and 22.5792 MHz audio codec clock in AV receivers and soundbars. IC Role / Device Role / Timing Role: Multi-frequency timing hub synchronizing heterogeneous SoCs and codecs within a single PCB domain. Use Value: Factory-programmed frequencies eliminate runtime configuration errors; independent VDDO pins match each subsystem's voltage rail.

HDMI Video Timing

USB Controller Clocking

Use Scenario: Generating precise pixel clocks (74.25 MHz) and audio sample clocks (24.576 MHz) for HDMI transmitters in set-top boxes and Blu-ray players.

IC Role / Device Role / Timing Role: Primary clock source replacing multiple XOs; provides synchronized, low-jitter clocks with static phase offset control.

Use Value: Eliminates board space and EMI from discrete oscillators while meeting HDMI CTS jitter limits (<150 ps pk-pk).

Use Scenario: Supplying 48 MHz USB 2.0 reference clock and 12 MHz suspend/resume clock to USB host controllers in residential gateways.

IC Role / Device Role / Timing Role: Single-device clock source for USB PHY layer timing, supporting both active and low-power states.

Use Value: Reduces component count vs. dual-XO solution; spread spectrum on 48 MHz output lowers radiated emissions during FCC testing.

Ethernet PHY Synchronization

Audio/Video Processor Interface

Use Scenario: Delivering 25 MHz or 28.322 MHz reference clocks to Ethernet PHYs (e.g., Broadcom BCM54210) in networking switches and routers.

IC Role / Device Role / Timing Role: Low-jitter clock generator with robust PSRR, immune to power rail noise from adjacent switch-mode regulators.

Use Value: Meets IEEE 802.3 jitter tolerance (≤1.5 UI) without external filtering; 70 ps pk-pk jitter ensures clean eye diagrams.

Use Scenario: Providing 33.333 MHz CPU clock, 27 MHz video processor clock, and 22.5792 MHz audio codec clock in AV receivers and soundbars.

IC Role / Device Role / Timing Role: Multi-frequency timing hub synchronizing heterogeneous SoCs and codecs within a single PCB domain.

Use Value: Factory-programmed frequencies eliminate runtime configuration errors; independent VDDO pins match each subsystem's voltage rail.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5350A-B-GT	Blank (unprogrammed) version requiring I²C configuration; same 10-MSOP package and 3-output architecture	Requires external microcontroller and firmware for initialization; unsuitable for systems lacking I²C or needing instant-on clocks	Select SI5350A-B05598-GTR when factory-programmed, pin-controlled operation is mandatory
Si5351A-B-GT	I²C-programmable 3-output variant with XTAL-only reference; supports higher max frequency (200 MHz) but lacks FS pin control and dual-frequency outputs	No hardware-based frequency switching; relies on software updates for clock changes - not glitchless	Choose Si5351A-B-GT only if design requires field-upgradable clock plans and has I²C resources available

Compared with Si5350A-B-GT and Si5351A-B-GT, SI5350A-B05598-GTR delivers deterministic, zero-latency clock startup and hardware-selectable dual frequencies - critical for consumer AV products where boot time and EMI compliance are non-negotiable.

Availability

SI5350A-B05598-GTR is available at Aetrix Electronics and suitable for HDMI video timing, USB controller clocking, and Ethernet PHY synchronization requiring stable component supply, long-term lifecycle assurance, and factory-traceable configurations.

Supply support for SI5350A-B05598-GTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs.

The Si5350A product line delivers factory-programmable, low-jitter clock generators for cost-sensitive consumer and networking applications - designed to replace multiple crystals and oscillators with a single configurable device.

FAQ

What reference crystal frequency does the SI5350A-B05598-GTR require?

The SI5350A-B05598-GTR requires a 25 MHz or 27 MHz fundamental-mode AT-cut crystal connected across XA and XB pins. It does not support external clock input (CLKIN) or voltage-controlled crystal oscillator (VCXO) references. Internal load capacitance options (0/6/8/10 pF) are configured during factory programming, eliminating need for external crystal capacitors in most cases.

Can the SI5350A-B05598-GTR generate two different frequencies on the same output pin?

Yes, the SI5350A-B05598-GTR supports dual-frequency operation (F1_x and F2_x) on CLK0, CLK1, and CLK2 via FS_0 and FS_1 control pins. When FS_0 is low, CLK0 outputs F1_0; when FS_0 is high, it outputs F2_0 - with zero-cycle glitchless transition. This capability is factory-programmed and does not require I²C interaction.

Does the SI5350A-B05598-GTR support HCSL-compatible output swing?

Yes, the SI5350A-B05598-GTR supports HCSL-compatible swing when VDDOA and/or VDDOB are set to 2.5 V and one of the complementary outputs (e.g., CLK0 or CLK1) is inverted using the INV function. This configuration meets JEDEC HCSL jitter specifications and is validated for PCIe Gen1 compatibility - but only in 10-MSOP and 20-QFN packages.

What is the maximum number of unique frequencies above 112.5 MHz the SI5350A-B05598-GTR can output simultaneously?

The SI5350A-B05598-GTR can output no more than two unique frequencies above 112.5 MHz at the same time. For example, 125 MHz on CLK0 and 130 MHz on CLK1 is permitted, but adding 150 MHz on CLK2 violates the specification. Multiple copies of the same high-frequency signal (e.g., 125 MHz on all three outputs) are allowed.

How is spread spectrum applied on the SI5350A-B05598-GTR, and which outputs support it?

Spread spectrum is selectable per output and only available on clocks derived from PLLA - not PLLB. It offers down-spread (–0.1% to –2.5%) or center-spread (±0.1% to ±1.5%) modulation at 30–33 kHz. The SSEN pin enables/disables spread spectrum globally. Spread spectrum reduces radiated EMI but is incompatible with PLLB-synchronized outputs like those used for static phase offset features.

SI5350A-B05598-GTR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 10-MSOP

SI5350A-B05598-GTR FAQ

1.How can I place an order for SI5350A-B05598-GTR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5350A-B05598-GTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5350A-B05598-GTR reliable?

The price and inventory of SI5350A-B05598-GTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5350A-B05598-GTR is usually 5 days.

3.What payment methods are accepted for SI5350A-B05598-GTR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5350A-B05598-GTR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5350A-B05598-GTR?

SI5350A-B05598-GTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5350A-B05598-GTR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5350A-B05598-GTR?

For technical support, including SI5350A-B05598-GTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5350A-B05598-GTR requirements.

6.How does Aetrix verify that SI5350A-B05598-GTR is sourced from the original manufacturer or authorized distributors?

All SI5350A-B05598-GTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5350A-B05598-GTR meets industry standards.

7.What is the process for return or replacement of SI5350A-B05598-GTR?

All SI5350A-B05598-GTR units undergo pre-shipment inspection (PSI). If there is an issue with SI5350A-B05598-GTR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5350A-B05598-GTR part is unused and in its original packaging.

Return procedure for SI5350A-B05598-GTR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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