Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5350A-B05801-GM

Name: SI5350A-B05801-GM
Brand: Skyworks Solutions Inc.
SKU: SI5350A-B05801-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5350A-B05801-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 20-VFQFN Exposed Pad

Datasheet:: SI5350A-B05801-GM.pdf

Description:: IC ANY FREQ ANY OUT XTAL 20QFN

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,120

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5350A-B05801-GM from Skyworks Solutions is a factory-programmed, pin-controlled CMOS clock generator delivering up to 8 independent output frequencies (2.5 kHz–200 MHz) with 0 ppm synthesis error, <70 ps pk-pk period jitter, and configurable spread spectrum on any output. It replaces multiple crystals/XOs in audio/video processors, HDMI interfaces, and Ethernet PHYs using a single 25 or 27 MHz crystal reference.

For engineers reviewing the SI5350A-B05801-GM datasheet, SI5350A-B05801-GM pinout, SI5350A-B05801-GM application, or SI5350A-B05801-GM equivalent, this device supports glitchless frequency switching via FS pins, HCSL-compatible outputs at 2.5 V VDDO, static phase offset control, and independent core/output voltage rails (1.8/2.5/3.3 V).

Technical Context

The SI5350A-B05801-GM implements a dual-PLL + eight fractional MultiSynth™ architecture, enabling simultaneous non-integer-related frequencies per output. Each MultiSynth divider supports two user-configurable frequencies (F1_x/F2_x) selected by FS_0/FS_1 pins for glitchless transitions.

It operates from a fixed 25 or 27 MHz crystal (XA/XB), supports spread spectrum only on PLLA-synchronized outputs, and provides separate VDD (core) and VDDOx (output buffer) supplies for level translation and PSRR optimization without external filtering.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	8 independent CMOS clock outputs (CLK0–CLK7)
Frequency range	2.5 kHz to 200 MHz per output; max two unique frequencies >112.5 MHz simultaneously
Period jitter	<70 ps pk-pk (typ), measured across all 8 outputs running at 33.33, 74.25, 27, 24.576, 22.5792, 28.322, 125, and 48 MHz
Core supply	1.8 V / 2.5 V / 3.3 V (±5% to ±10%), with independent VDDOx rails per output group
Reference input	25 MHz or 27 MHz fundamental-mode AT-cut crystal (XA/XB); no external load caps required for 6–10 pF CL
Spread spectrum	Selectable per-output: down-spread (–0.1% to –2.5%) or center-spread (±0.1% to ±1.5%) at 30–33 kHz modulation rate
Power consumption	25 mA typ (all 8 outputs enabled), 50 µA in power-down mode (PDN = high)

Pinout & Package

SI5350A-B05801-GM is packaged in a 20-pin QFN (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Rev. 1.2 datasheet Section 7.1.

Pin/Terminal	Circuit Role	Design Meaning
XA, XB	Crytal oscillator inputs	Accept 25 or 27 MHz fundamental-mode crystal; internal 0/6/8/10 pF load capacitance selectable via ClockBuilder Pro
CLK0–CLK7	CMOS clock outputs	Individually configurable frequency, drive strength, invert/non-invert, and spread spectrum; each pair shares VDDOx rail
VDDOA–VDDOD	Output buffer supplies	Four independent 1.8/2.5/3.3 V rails: VDDOA (CLK0/1), VDDOB (CLK2/3), VDDOC (CLK4/5), VDDOD (CLK6/7)
VDD, GND	Core power and ground	1.8/2.5/3.3 V core supply; must be powered before or concurrently with all VDDOx rails
P0–P4	Configurable control pins	P0: OEB_0 (output enable for CLK0); P1/P2: OEB_1/OEB_2; P3: SSEN; P4: PDN - all support 0.3×VDD/0.7×VDD logic thresholds

Key Features

Feature	Design Value
Factory-programmed configuration	Preloaded with exact frequency plan (SI5350A-B05801-GM), eliminating I²C programming hardware and firmware overhead
Glitchless frequency switching	F1_x/F2_x dual-frequency mode on CLK0–CLK2 enables zero-cycle transition between rates (e.g., 74.25 MHz ↔ 74.25/1.001 MHz) via FS_0/FS_1 pins
HCSL-compatible outputs	Configurable 2.5 V VDDO + 50 Ω output impedance + complementary inverted clock enables drop-in replacement for HCSL sources (10-MSOP/20-QFN only)
Independent voltage domains	Separate VDD (core) and VDDOx (output) rails allow mixed-voltage system interfacing (e.g., 1.8 V core + 3.3 V I/O) without level shifters
Low EMI spread spectrum	Per-output spread spectrum with user-selectable deviation (±0.1–1.5%) and fixed 31.5 kHz modulation reduces peak radiated emissions without affecting timing margin

Applications

HDMI Audio/Video Processor Timing	Residential Gateway Ethernet PHY Clocking
Use Scenario: Synchronizing HDMI transmitter (74.25 MHz), audio codec (24.576 MHz), and video processor (48 MHz) in set-top boxes. IC Role / Device Role / Timing Role: Single-chip multi-frequency clock source replacing three discrete XOs and reducing board space by 60%. Use Value: Eliminates inter-clock skew, enables shared crystal reference for deterministic phase relationships, and cuts BOM cost vs. multiple oscillators.	Use Scenario: Driving 100/1000BASE-T Ethernet PHY (25 MHz), USB 2.0 controller (48 MHz), and CPU (33.333 MHz) in home gateways. IC Role / Device Role / Timing Role: Factory-configured 4-output clock generator with independent VDDO rails for mixed-voltage PHY and controller interfaces. Use Value: Reduces layout complexity by consolidating clocks onto one IC with programmable rise/fall times and <70 ps jitter for clean signal integrity.
Printers & Scanners System Clocking	Handheld Instrumentation Signal Generation
Use Scenario: Providing 27 MHz (image sensor), 22.5792 MHz (audio DAC), and 28.322 MHz (motor controller) in multifunction printers. IC Role / Device Role / Timing Role: Pin-controlled clock generator with FS_0/FS_1 enabling dual-rate operation for variable-speed scanning modes. Use Value: Glitchless frequency switching allows real-time adjustment of scan resolution without system reset or clock interruption.	Use Scenario: Generating precise test tones (125 MHz sampling clock, 24.576 MHz DAC reference, 48 MHz MCU clock) in portable oscilloscopes. IC Role / Device Role / Timing Role: Low-jitter, factory-programmed clock source with spread spectrum disabled for measurement-grade stability. Use Value: <40 ps pk-pk period jitter (4-output config) ensures sub-LSB timing accuracy in high-resolution ADC/DAC paths.

HDMI Audio/Video Processor Timing

Residential Gateway Ethernet PHY Clocking

Use Scenario: Synchronizing HDMI transmitter (74.25 MHz), audio codec (24.576 MHz), and video processor (48 MHz) in set-top boxes.

IC Role / Device Role / Timing Role: Single-chip multi-frequency clock source replacing three discrete XOs and reducing board space by 60%.

Use Value: Eliminates inter-clock skew, enables shared crystal reference for deterministic phase relationships, and cuts BOM cost vs. multiple oscillators.

Use Scenario: Driving 100/1000BASE-T Ethernet PHY (25 MHz), USB 2.0 controller (48 MHz), and CPU (33.333 MHz) in home gateways.

IC Role / Device Role / Timing Role: Factory-configured 4-output clock generator with independent VDDO rails for mixed-voltage PHY and controller interfaces.

Use Value: Reduces layout complexity by consolidating clocks onto one IC with programmable rise/fall times and <70 ps jitter for clean signal integrity.

Printers & Scanners System Clocking

Handheld Instrumentation Signal Generation

Use Scenario: Providing 27 MHz (image sensor), 22.5792 MHz (audio DAC), and 28.322 MHz (motor controller) in multifunction printers.

IC Role / Device Role / Timing Role: Pin-controlled clock generator with FS_0/FS_1 enabling dual-rate operation for variable-speed scanning modes.

Use Value: Glitchless frequency switching allows real-time adjustment of scan resolution without system reset or clock interruption.

Use Scenario: Generating precise test tones (125 MHz sampling clock, 24.576 MHz DAC reference, 48 MHz MCU clock) in portable oscilloscopes.

IC Role / Device Role / Timing Role: Low-jitter, factory-programmed clock source with spread spectrum disabled for measurement-grade stability.

Use Value: <40 ps pk-pk period jitter (4-output config) ensures sub-LSB timing accuracy in high-resolution ADC/DAC paths.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5350A-B05802-GM	Same 20-QFN package and 8-output architecture, but factory-programmed for 27 MHz crystal reference (vs. 25 MHz for SI5350A-B05801-GM)	Requires 27 MHz crystal; not interchangeable without crystal change and revalidation of load capacitance	Select when 27 MHz XTAL is already used in design or preferred for lower phase noise at higher frequencies
Si5351A-B-GM	I²C-programmable (not factory-programmed), 8-output, same frequency range but higher typical period jitter (95 ps pk-pk vs. 70 ps)	Suitable for prototyping or field-upgradable systems; requires microcontroller I²C interface and configuration firmware	Choose for flexibility in frequency tuning post-deployment, accepting higher jitter and added software complexity

Compared with SI5350A-B05801-GM, Si5350A-B05802-GM offers identical performance with a different crystal frequency, while Si5351A-B-GM trades factory simplicity for runtime programmability and slightly degraded jitter - making SI5350A-B05801-GM optimal for cost-sensitive, high-volume production where fixed timing is verified.

Availability

SI5350A-B05801-GM is available at Aetrix Electronics and suitable for HDMI transceivers, residential gateways, and printer/scanner systems requiring stable component supply, long-term lifecycle support, and factory-verified timing accuracy.

Supply support for SI5350A-B05801-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, and timing markets.

The Si5350A family delivers factory-programmed, low-jitter clock generation for cost-sensitive consumer and networking applications - designed to replace multiple crystals and oscillators with a single configurable IC.

FAQ

What crystal frequency does SI5350A-B05801-GM require?

SI5350A-B05801-GM is factory-programmed for use with a 25 MHz fundamental-mode AT-cut crystal connected to XA/XB pins. The device's internal load capacitance (6/8/10 pF) eliminates need for external capacitors unless the crystal specifies 12 pF CL, in which case ≤2 pF external caps are added. Operation with 27 MHz crystals requires a different part number (e.g., SI5350A-B05802-GM).

Does SI5350A-B05801-GM support HCSL-compatible outputs?

Yes, SI5350A-B05801-GM supports HCSL-compatible swing when configured with 2.5 V on the relevant VDDO rail (e.g., VDDOA = 2.5 V for CLK0/CLK1) and paired with an external 511 Ω pull-up and 240 Ω termination resistor per output. This capability is validated for the 20-QFN package and requires one output in each pair to be inverted via ClockBuilder Pro configuration.

How many frequencies can SI5350A-B05801-GM generate above 112.5 MHz simultaneously?

SI5350A-B05801-GM can output no more than two *unique* frequencies above 112.5 MHz at once - for example, 125 MHz on CLK0 and 130 MHz on CLK1 is permitted, but adding 150 MHz on CLK2 violates the specification. Multiple outputs may replicate the same high-frequency signal (e.g., 125 MHz on CLK0–CLK3), preserving timing consistency across parallel data paths.

What is the power-down current of SI5350A-B05801-GM?

When the PDN pin is driven high, SI5350A-B05801-GM enters full power-down mode with a maximum supply current of 50 µA. This state disables all PLLs, MultiSynths, and outputs while retaining factory-programmed configuration. Power-up time from PDN assertion to valid clock output is ≤10 ms (typical 2 ms) per Table 5 in the datasheet.

Can SI5350A-B05801-GM generate different frequencies on CLK0 and CLK1 with glitchless switching?

Yes, SI5350A-B05801-GM supports glitchless frequency switching on CLK0 and CLK1 using the FS_0 and FS_1 pins. Each output is preconfigured with two frequencies (F1_x/F2_x) during factory programming; asserting FS_0 low selects F1_0 on CLK0, while driving it high selects F2_0 - with zero-cycle transition and no runt pulses or phase discontinuity.

SI5350A-B05801-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 20-VFQFN Exposed Pad

Packaging:: Strip

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 20-QFN (4x4)

SI5350A-B05801-GM FAQ

1.How can I place an order for SI5350A-B05801-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5350A-B05801-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5350A-B05801-GM reliable?

The price and inventory of SI5350A-B05801-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5350A-B05801-GM is usually 5 days.

3.What payment methods are accepted for SI5350A-B05801-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5350A-B05801-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5350A-B05801-GM?

SI5350A-B05801-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5350A-B05801-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5350A-B05801-GM?

For technical support, including SI5350A-B05801-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5350A-B05801-GM requirements.

6.How does Aetrix verify that SI5350A-B05801-GM is sourced from the original manufacturer or authorized distributors?

All SI5350A-B05801-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5350A-B05801-GM meets industry standards.

7.What is the process for return or replacement of SI5350A-B05801-GM?

All SI5350A-B05801-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5350A-B05801-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5350A-B05801-GM part is unused and in its original packaging.

Return procedure for SI5350A-B05801-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…