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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5350A-B06299-GM

Name: SI5350A-B06299-GM
Brand: Skyworks Solutions Inc.
SKU: SI5350A-B06299-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5350A-B06299-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 20-VFQFN Exposed Pad

Datasheet:: SI5350A-B06299-GM.pdf

Description:: IC ANY FREQ ANY OUT XTAL 20QFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5350A-B06299-GM from Skyworks Solutions is a factory-programmed, pin-controlled CMOS clock generator with 8 independent outputs, synthesizing frequencies from 2.5 kHz to 200 MHz using a 25/27 MHz crystal reference, delivering 0 ppm frequency error and <70 ps pk-pk period jitter-used in HDMI video processors, USB controllers, and Ethernet PHYs for multi-clock domain synchronization.

For engineers reviewing the SI5350A-B06299-GM datasheet, SI5350A-B06299-GM pinout, SI5350A-B06299-GM application, or SI5350A-B06299-GM equivalent, key selection criteria include output count (8), PLL+MultiSynth architecture, spread spectrum enable per output, configurable VDDO voltage per bank, and HCSL-compatible swing support at 2.5 V VDDO.

Technical Context

The SI5350A-B06299-GM implements dual high-frequency PLLs (PLLA and PLLB) with eight independent fractional MultiSynth™ dividers-one per output-enabling simultaneous generation of non-integer-related frequencies up to 200 MHz. PLLA supports spread spectrum modulation (±0.1% to ±1.5%, 31.5 kHz rate); PLLB does not.

It accepts only a fixed 25 MHz or 27 MHz crystal on XA/XB inputs (no external CLKIN), uses pin-strapped control (P0–P4) for OEB, PDN, FS_0/FS_1, and SSEN, and supports static phase offset, rise/fall time control, and per-output drive strength via 50 Ω output impedance configuration.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	8 independent CMOS clock outputs (CLK0–CLK7), each programmable to unique frequencies
Frequency range	2.5 kHz to 200 MHz per output; only two unique frequencies >112.5 MHz simultaneously allowed
Reference input	25 MHz or 27 MHz fundamental-mode AT-cut crystal only (XA/XB); no external clock input support
Period jitter	<70 ps pk-pk (typ), measured across all 8 outputs running at 33.33, 74.25, 27, 24.576, 22.5792, 28.322, 125, and 48 MHz
Core supply	1.8 V / 2.5 V / 3.3 V (±5–10%), with independent VDDOx supplies (1.8/2.5/3.3 V) per output bank for level translation
Spread spectrum	Selectable per-output down-spread (–0.1% to –2.5%) or center-spread (±0.1% to ±1.5%) at 31.5 kHz modulation rate
Power consumption	25 mA (typ) core current with all 8 outputs enabled; 50 µA in power-down mode (PDN = high)

Pinout & Package

SI5350A-B06299-GM is packaged in a 20-pin QFN (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.2 datasheet Section 7.1.

Pin/Terminal	Circuit Role	Design Meaning
GND	Ground reference	Common return for core and output buffers; requires low-inductance connection to PCB ground plane
VDD	Core supply	1.8/2.5/3.3 V supply for PLLs, logic, and MultiSynths; must be powered before or concurrently with VDDOx
VDDOA–VDDOD	Output buffer supplies	Four independent 1.8/2.5/3.3 V supplies-each powers two outputs (e.g., VDDOA → CLK0/CLK1)-enabling mixed-voltage I/O
CLK0–CLK7	CMOS clock outputs	Eight single-ended outputs; configurable for HCSL-compatible swing when corresponding VDDOx = 2.5 V and INV enabled
XA / XB	Crystal oscillator inputs	Differential crystal interface for 25/27 MHz AT-cut crystals; internal load capacitance selectable (0/6/8/10 pF) via ClockBuilder Pro
P0–P4	Configurable control pins	Programmable as OEB_0/1/2 (output enables), PDN (global shutdown), FS_0/FS_1 (dual-frequency select), or SSEN (spread spectrum enable)

Key Features

Feature	Design Value
Factory-programmed any-frequency synthesis	Delivers exact user-defined frequencies (e.g., 74.25 MHz, 22.5792 MHz, 28.322 MHz) with 0 ppm error-no post-manufacture I²C programming required
Glitchless frequency switching	FS_0/FS_1 pins enable seamless transition between two preconfigured frequencies (F1_x/F2_x) on CLK0–CLK2 without clock interruption or metastability
HCSL-compatible output mode	When VDDOA = 2.5 V and CLK0/CLK1 are configured with complementary INV, achieves HCSL-level swing (≈800 mVpp) into 50 Ω loads-valid for 10-MSOP and 20-QFN packages only
Per-output spread spectrum control	Independent SSEN-linked or register-based spread spectrum enable/disable per output driven by PLLA-reduces EMI peak amplitude without altering system timing margins
Low-power operation with dynamic control	Power-down (PDN) reduces current to 50 µA; unused outputs can be disabled individually via OEB pins to minimize active current (25 mA typ full-load)

Applications

HDMI Video Processing	USB 2.0 Host Controller
Use Scenario: Synchronizing pixel clock (74.25 MHz), audio clock (24.576 MHz), and auxiliary timing (48 MHz) in set-top boxes and Blu-ray players. IC Role / Device Role / Timing Role: Replaces three discrete crystals/XOs with a single programmable source, eliminating board space and BOM cost. Use Value: Enables precise inter-clock phase alignment and eliminates crystal aging drift across domains-critical for lip-sync accuracy and jitter-sensitive HDMI TMDS lanes.	Use Scenario: Providing 48 MHz USB PHY clock and 24.576 MHz audio subsystem clock in residential gateways and printers. IC Role / Device Role / Timing Role: Delivers low-jitter (<70 ps pk-pk), spread-spectrum-enabled 48 MHz clock meeting USB 2.0 EMI requirements. Use Value: Reduces radiated emissions without external filtering-avoids costly ferrite beads or shielded enclosures while maintaining full-speed USB compliance.
Ethernet PHY Timing	Multi-Core CPU Reference
Use Scenario: Generating 25 MHz, 125 MHz, and 28.322 MHz clocks for 10/100/1000BASE-T PHYs and associated MAC interfaces. IC Role / Device Role / Timing Role: Supplies synchronized, low-phase-noise clocks to multiple PHY instances sharing a common crystal reference. Use Value: Eliminates inter-PHY skew and jitter accumulation-improves bit-error-rate (BER) margin and enables deterministic packet latency in switch fabric designs.	Use Scenario: Delivering 33.333 MHz system bus clock and 27 MHz peripheral clock to ARM-based SoCs in industrial embedded controllers. IC Role / Device Role / Timing Role: Acts as primary timing source replacing legacy XO + divider chains, with pin-selectable frequency modes for low-power sleep states. Use Value: FS_0/FS_1 pins allow runtime switching between performance (33.333 MHz) and idle (27 MHz) modes-reducing dynamic power by >15% during low-activity periods.

HDMI Video Processing

USB 2.0 Host Controller

Use Scenario: Synchronizing pixel clock (74.25 MHz), audio clock (24.576 MHz), and auxiliary timing (48 MHz) in set-top boxes and Blu-ray players.

IC Role / Device Role / Timing Role: Replaces three discrete crystals/XOs with a single programmable source, eliminating board space and BOM cost.

Use Value: Enables precise inter-clock phase alignment and eliminates crystal aging drift across domains-critical for lip-sync accuracy and jitter-sensitive HDMI TMDS lanes.

Use Scenario: Providing 48 MHz USB PHY clock and 24.576 MHz audio subsystem clock in residential gateways and printers.

IC Role / Device Role / Timing Role: Delivers low-jitter (<70 ps pk-pk), spread-spectrum-enabled 48 MHz clock meeting USB 2.0 EMI requirements.

Use Value: Reduces radiated emissions without external filtering-avoids costly ferrite beads or shielded enclosures while maintaining full-speed USB compliance.

Ethernet PHY Timing

Multi-Core CPU Reference

Use Scenario: Generating 25 MHz, 125 MHz, and 28.322 MHz clocks for 10/100/1000BASE-T PHYs and associated MAC interfaces.

IC Role / Device Role / Timing Role: Supplies synchronized, low-phase-noise clocks to multiple PHY instances sharing a common crystal reference.

Use Value: Eliminates inter-PHY skew and jitter accumulation-improves bit-error-rate (BER) margin and enables deterministic packet latency in switch fabric designs.

Use Scenario: Delivering 33.333 MHz system bus clock and 27 MHz peripheral clock to ARM-based SoCs in industrial embedded controllers.

IC Role / Device Role / Timing Role: Acts as primary timing source replacing legacy XO + divider chains, with pin-selectable frequency modes for low-power sleep states.

Use Value: FS_0/FS_1 pins allow runtime switching between performance (33.333 MHz) and idle (27 MHz) modes-reducing dynamic power by >15% during low-activity periods.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5351A-B-GM	I²C-programmable (not factory-configured); 8 outputs; supports external CLKIN (unlike SI5350A-B06299-GM's crystal-only input)	Better suited for prototyping or field-upgradable systems requiring dynamic reconfiguration	Choose Si5351A-B-GM if design requires post-deployment frequency changes; SI5350A-B06299-GM is optimal for fixed, cost-sensitive production units.
CDCE906PWR	6-output, 3.3 V only; uses internal PLL with integer-N dividers (no fractional synthesis); max 230 MHz output	Lacks 0 ppm exact synthesis and per-output spread spectrum; limited to integer-related frequencies	CDCE906PWR fits simpler, lower-cost applications where frequency flexibility and ultra-low jitter are secondary to minimal BOM count.

Compared with Si5351A-B-GM and CDCE906PWR, SI5350A-B06299-GM delivers superior frequency precision (0 ppm vs. ppm-level error), lower jitter (<70 ps vs. ≥100 ps), and dedicated crystal-only architecture ideal for high-volume, fixed-function consumer electronics-without I²C bus overhead or external clock dependency.

Availability

SI5350A-B06299-GM is available at Aetrix Electronics and suitable for HDMI video processing, USB host controller timing, Ethernet PHY synchronization, and multi-core CPU reference applications requiring stable component supply, long-term lifecycle assurance, and factory-programmed consistency.

Supply support for SI5350A-B06299-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for wireless infrastructure, automotive, and industrial markets.

The SI5350A-B06299-GM belongs to Skyworks' Si5350 family of factory-programmable clock generators, designed specifically to replace multiple crystals and oscillators in cost-sensitive, high-volume consumer and networking equipment-emphasizing zero-error synthesis, low jitter, and minimal layout complexity.

FAQ

What reference clock does the SI5350A-B06299-GM require?

The SI5350A-B06299-GM requires a 25 MHz or 27 MHz fundamental-mode AT-cut crystal connected across XA and XB pins. It does not accept external clock signals-only crystal reference. Internal load capacitance (0/6/8/10 pF) is configurable via ClockBuilder Pro, and optional external capacitors ≤2 pF may be added for crystals requiring 12 pF load.

How many outputs does the SI5350A-B06299-GM support, and what package is used?

The SI5350A-B06299-GM supports 8 independent CMOS clock outputs (CLK0–CLK7) and is supplied in a 20-pin QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. This matches the 8-output variant described in Skyworks' Si5350A-B datasheet Section 1 and Table 1 ordering guide.

Can the SI5350A-B06299-GM generate HCSL-compatible outputs?

Yes-the SI5350A-B06299-GM supports HCSL-compatible swing on CLK0/CLK1 when VDDOA is set to 2.5 V and one output is inverted (INV function enabled). This requires external 511 Ω and 240 Ω resistors per output pair and is validated only for 10-MSOP and 20-QFN packages-not the 16-QFN variant.

Does the SI5350A-B06299-GM support spread spectrum on all outputs?

No-spread spectrum is only available on outputs derived from PLLA. Outputs synchronized to PLLB do not support spread spectrum. The SI5350A-B06299-GM allows per-output enable/disable via SSEN pin or internal register, with modulation rates fixed at 31.5 kHz and deviation selectable from ±0.1% to ±1.5% (center) or –0.1% to –2.5% (down).

What is the maximum number of unique high-frequency outputs supported by the SI5350A-B06299-GM?

The SI5350A-B06299-GM allows only two unique frequencies above 112.5 MHz simultaneously-for example, 125 MHz on CLK0 and 130 MHz on CLK1-but permits replication (e.g., 125 MHz on CLK0–CLK3 and 130 MHz on CLK4–CLK7). This constraint arises from internal PLL bandwidth and MultiSynth resource allocation.

SI5350A-B06299-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 20-VFQFN Exposed Pad

Packaging:: Strip

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 20-QFN (4x4)

SI5350A-B06299-GM FAQ

1.How can I place an order for SI5350A-B06299-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5350A-B06299-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5350A-B06299-GM reliable?

The price and inventory of SI5350A-B06299-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5350A-B06299-GM is usually 5 days.

3.What payment methods are accepted for SI5350A-B06299-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5350A-B06299-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5350A-B06299-GM?

SI5350A-B06299-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5350A-B06299-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5350A-B06299-GM?

For technical support, including SI5350A-B06299-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5350A-B06299-GM requirements.

6.How does Aetrix verify that SI5350A-B06299-GM is sourced from the original manufacturer or authorized distributors?

All SI5350A-B06299-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5350A-B06299-GM meets industry standards.

7.What is the process for return or replacement of SI5350A-B06299-GM?

All SI5350A-B06299-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5350A-B06299-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5350A-B06299-GM part is unused and in its original packaging.

Return procedure for SI5350A-B06299-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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