Skyworks Solutions Inc. SI5350A-B06405-GTR
- Part No.:
- SI5350A-B06405-GTR
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
SI5350A-B06405-GTR.pdf
- Description:
- IC ANY FREQ ANY OUT XTAL 10MSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5350A-B06405-GTR from Skyworks Solutions is a factory-programmed, pin-controlled CMOS clock generator delivering three independent output clocks (CLK0–CLK2) with 0 ppm frequency error across 2.5 kHz–200 MHz. It uses a 25 or 27 MHz crystal reference, supports per-output spread spectrum modulation, and operates with independent core (1.8/2.5/3.3 V) and output (1.8/2.5/3.3 V) supply rails. It replaces multiple discrete crystals in audio/video timing systems.
For engineers reviewing the SI5350A-B06405-GTR datasheet, SI5350A-B06405-GTR pinout, SI5350A-B06405-GTR application, or SI5350A-B06405-GTR equivalent, key selection criteria include its 3-output 10-MSOP package, glitchless dual-frequency capability on CLK0–CLK2 via FS_0/FS_1 pins, HCSL-compatible swing support at 2.5 V VDDO, and factory-programmed configuration eliminating I²C initialization.
Technical Context
The SI5350A-B06405-GTR implements a dual-PLL + eight fractional MultiSynth architecture-though only three outputs are enabled in this variant-enabling simultaneous synthesis of non-integer-related frequencies. Each output is driven by an independent MultiSynth divider with configurable F1_x/F2_x frequency pairs selectable via dedicated control pins.
It accepts only a fixed-frequency crystal (25 or 27 MHz) at XA/XB inputs, lacks CLKIN capability, and routes all outputs through a single VDDOA supply rail. Spread spectrum is available only on PLLA-sourced outputs and is controlled globally via SSEN, not per-output.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Outputs | 3 CMOS clock outputs (CLK0–CLK2), factory-configured with specific frequencies |
| Frequency Range | 2.5 kHz to 200 MHz per output; only two unique frequencies >112.5 MHz allowed simultaneously |
| Output Jitter (pk-pk) | <70 ps typical period jitter (10-MSOP, all outputs active), measured over 10k cycles |
| Supply Voltages | Core VDD: 1.71–1.89 V / 2.25–2.75 V / 3.0–3.6 V; Output VDDOA: same ranges, independently set |
| Crystal Reference | 25 MHz or 27 MHz fundamental-mode AT-cut crystal; internal load capacitance options (0/6/8/10 pF) |
| Control Pins | P0 (FS_0), P1 (FS_1), P2 (OEB_0), P3 (OEB_1), P4 (OEB_2); SSEN and PDN not assigned in this variant |
| Package | 10-pin MSOP (3.0 × 4.9 mm), thermal resistance θJA = 150 °C/W (2-layer board) |
Pinout & Package
SI5350A-B06405-GTR is housed in a 10-pin MSOP package (3.0 × 4.9 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments follow the standard Si5350A 10-MSOP layout: pins 1–10 correspond to GND, CLK2, VDDOA, CLK1, CLK0, VDD, XA, XB, P0, P1 - with P2–P4 unassigned in this configuration.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GND (Pin 1) | Ground reference | Primary analog/digital return for core and outputs; must be low-impedance connection to PCB ground plane |
| CLK2 (Pin 2) | Output clock 2 | Factory-programmed CMOS clock signal; level-shifted by VDDOA; supports invert/non-invert and high-Z disable |
| VDDOA (Pin 3) | Output buffer supply | Single rail powering all three outputs; sets logic high level and drive strength (50 Ω default impedance) |
| CLK1 (Pin 4) | Output clock 1 | Factory-programmed CMOS clock; supports F1_1/F2_1 dual-frequency selection via P0/P1 |
| CLK0 (Pin 5) | Output clock 0 | Factory-programmed CMOS clock; supports F1_0/F2_0 dual-frequency selection via P0/P1 |
| VDD (Pin 6) | Core supply | Independent voltage for PLLs, dividers, and logic; must power up before or simultaneously with VDDOA |
| XA (Pin 7) | Crytal input A | Connects to one terminal of 25/27 MHz crystal; internal oscillator circuit drives crystal directly |
| XB (Pin 8) | Crytal input B | Connects to other crystal terminal; floating not permitted-must be connected to crystal |
| P0 (Pin 9) | Frequency select 0 | Binary control input selecting F1_x or F2_x on CLK0–CLK2; pulled high internally if unused |
| P1 (Pin 10) | Frequency select 1 | Second binary control input enabling 4-state frequency selection (F1/F2 per output); pulled high internally if unused |
Key Features
| Feature | Design Value |
|---|---|
| Factory-programmed configuration | Eliminates I²C bus, external EEPROM, and firmware initialization-device powers up with valid clocks immediately |
| Dual-frequency outputs (F1_x/F2_x) | Enables dynamic clock rate switching (e.g., 74.25 MHz ↔ 74.25/1.001 MHz) without glitches or software intervention |
| HCSL-compatible swing | Configurable via 2.5 V VDDOA and external resistor network (511 Ω/240 Ω) to meet PCIe Gen1 and SATA timing requirements |
| Independent VDD/VDDOA rails | Allows interfacing with mixed-voltage SoCs (e.g., 1.8 V core logic + 3.3 V legacy peripherals) without level shifters |
| Low-power operation | 20–30 mA typical core current with 3 outputs active; 50 µA power-down current when PDN asserted (if enabled) |
Applications
| Audio/Video Timing | Residential Gateway |
|---|---|
Use Scenario: HDMI transmitter, audio codec, and video processor require synchronized but non-integer-related clocks (e.g., 74.25 MHz, 24.576 MHz, 48 MHz). IC Role / Device Role / Timing Role: Single-source, multi-frequency clock generator replacing three discrete crystals and reducing board space. Use Value: Eliminates crystal matching tolerances and board-level skew; enables precise phase alignment between audio and video domains. | Use Scenario: DSL/Cable gateway SoC needs separate clocks for Ethernet PHY (25 MHz), USB controller (48 MHz), and CPU (33.333 MHz). IC Role / Device Role / Timing Role: Factory-configured triple-clock source with guaranteed startup timing and no I²C dependency. Use Value: Reduces BOM count and boot-time clock initialization complexity; supports spread spectrum on Ethernet clock to pass FCC Class B emissions. |
| Printers & Scanners | Handheld Instrumentation |
Use Scenario: Laser printer controller requires 27 MHz for image processing, 22.5792 MHz for audio feedback, and 28.322 MHz for motor control. IC Role / Device Role / Timing Role: Low-cost, fixed-configuration clock generator with crystal-based stability and minimal external components. Use Value: Avoids temperature drift issues of standalone oscillators; enables cost-effective replacement of XO + buffer solutions. | Use Scenario: Portable oscilloscope FPGA needs 125 MHz sampling clock, 48 MHz USB interface clock, and 27 MHz ADC reference-all from one compact timing IC. IC Role / Device Role / Timing Role: Space-constrained, low-power clock source with factory-tuned jitter performance and fast power-up (<2 ms). Use Value: Meets <95 ps pk-pk period jitter requirement at 125 MHz while consuming <25 mA total supply current. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5350A-B-GT | Blank (unprogrammed) 10-MSOP variant requiring ClockBuilder Pro configuration and I²C programming at system startup | Requires microcontroller firmware support and external EEPROM; unsuitable for boot-critical clocks | Select SI5350A-B06405-GTR when deterministic power-on clock delivery is required without host intervention |
| Si5351A-B-GT | I²C-programmable 3-output variant with XTAL-only reference; supports higher max frequency (200 MHz vs. 160 MHz for some outputs) but higher typical jitter (110 ps vs. 70 ps) | Designed for flexible prototyping and field updates; lacks factory-set dual-frequency capability on all outputs | Select SI5350A-B06405-GTR when production volume, EMI control via spread spectrum, and pin-strapped frequency selection are mandatory |
Compared with Si5350A-B-GT and Si5351A-B-GT, SI5350A-B06405-GTR delivers guaranteed startup timing, lower jitter, and hardware-selectable frequencies-making it optimal for cost-sensitive, high-reliability embedded systems where firmware initialization is undesirable or unavailable.
Availability
SI5350A-B06405-GTR is available at Aetrix Electronics and suitable for audio/video timing, residential gateways, printers/scanners, and handheld instrumentation requiring stable component supply and factory-verified clock configurations.
Supply support for SI5350A-B06405-GTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with emphasis on performance, integration, and reliability.
The Si5350A-B product line delivers factory-programmable, low-jitter clock generation for cost-sensitive consumer and embedded applications-designed to replace multiple crystals and oscillators while maintaining sub-100 ps jitter and flexible voltage operation.
FAQ
What reference crystal frequency does the SI5350A-B06405-GTR require?
The SI5350A-B06405-GTR requires either a 25 MHz or 27 MHz fundamental-mode AT-cut crystal connected across XA and XB pins. Internal load capacitance options (0/6/8/10 pF) are configurable via ClockBuilder Pro during programming; external capacitors ≤2 pF may be added for crystals requiring 12 pF load. The SI5350A-B06405-GTR does not accept external clock signals at the XTAL inputs.
Does the SI5350A-B06405-GTR support spread spectrum on all three outputs?
Yes, the SI5350A-B06405-GTR supports spread spectrum modulation on all three outputs (CLK0–CLK2), provided they are sourced from PLLA. Spread spectrum deviation is selectable in 0.1% steps (–0.1% to –2.5% down-spread or ±0.1% to ±1.5% center-spread) with a fixed 31.5 kHz modulation rate. Outputs derived from PLLB do not support spread spectrum.
Can the SI5350A-B06405-GTR generate two different frequencies on the same output pin?
Yes, the SI5350A-B06405-GTR supports dual-frequency operation on all three outputs (CLK0–CLK2) using the factory-assigned P0 (FS_0) and P1 (FS_1) pins. These pins select between pre-programmed F1_x and F2_x frequencies per output-enabling glitchless transitions (e.g., 74.25 MHz ↔ 74.25/1.001 MHz) without software or I²C involvement. This capability is intrinsic to the SI5350A-B06405-GTR's pin-strapped configuration.
What is the maximum output frequency the SI5350A-B06405-GTR can deliver on each clock?
The SI5350A-B06405-GTR supports output frequencies from 2.5 kHz up to 200 MHz on each of CLK0–CLK2. However, only two unique frequencies above 112.5 MHz may be active simultaneously-for example, 125 MHz on CLK0 and 130 MHz on CLK1 is permitted, but adding 150 MHz on CLK2 violates the specification. Multiple instances of the same high-frequency clock (e.g., 125 MHz on all three outputs) are allowed.
Is the SI5350A-B06405-GTR compatible with HCSL signaling standards?
Yes, the SI5350A-B06405-GTR supports HCSL-compatible swing when VDDOA is set to 2.5 V and external termination resistors (511 Ω pull-down, 240 Ω AC-coupled) are applied per output pair. This configuration meets PCIe Gen1 jitter and amplitude requirements. HCSL mode is supported only in the 10-MSOP and 20-QFN packages-not the 16-QFN variant-and requires inversion of one clock in the pair to form a differential signal.
SI5350A-B06405-GTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- -
- PLL:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Divider/Multiplier:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 10-MSOP
SI5350A-B06405-GTR FAQ
1.How can I place an order for SI5350A-B06405-GTR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5350A-B06405-GTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5350A-B06405-GTR reliable?
The price and inventory of SI5350A-B06405-GTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5350A-B06405-GTR is usually 5 days.
3.What payment methods are accepted for SI5350A-B06405-GTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5350A-B06405-GTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5350A-B06405-GTR?
SI5350A-B06405-GTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5350A-B06405-GTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5350A-B06405-GTR?
For technical support, including SI5350A-B06405-GTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5350A-B06405-GTR requirements.
6.How does Aetrix verify that SI5350A-B06405-GTR is sourced from the original manufacturer or authorized distributors?
All SI5350A-B06405-GTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5350A-B06405-GTR meets industry standards.
7.What is the process for return or replacement of SI5350A-B06405-GTR?
All SI5350A-B06405-GTR units undergo pre-shipment inspection (PSI). If there is an issue with SI5350A-B06405-GTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5350A-B06405-GTR part is unused and in its original packaging.
Return procedure for SI5350A-B06405-GTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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