Skyworks Solutions Inc. SI5350A-B06876-GTR
- Part No.:
- SI5350A-B06876-GTR
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
SI5350A-B06876-GTR.pdf
- Description:
- IC ANY FREQ ANY OUT XTAL 10MSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,688
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Product details
Overview
SI5350A-B06876-GTR from Skyworks Solutions is a factory-programmed, pin-controlled CMOS clock generator delivering three independent output clocks (CLK0–CLK2) with exact frequency synthesis from 2.5 kHz to 200 MHz, 0 ppm error, <70 ps pk-pk period jitter, and spread spectrum support - used in HDMI audio/video timing, USB controller clocking, and Ethernet PHY synchronization.
For engineers reviewing the SI5350A-B06876-GTR datasheet, SI5350A-B06876-GTR pinout, SI5350A-B06876-GTR application, or SI5350A-B06876-GTR equivalent, key selection criteria include its 10-pin MSOP package, dual-frequency per output capability via FS_0/FS_1 pins, 25/27 MHz crystal reference requirement, and HCSL-compatible swing support at 2.5 V VDDO.
Technical Context
The SI5350A-B06876-GTR implements a dual-PLL + eight fractional MultiSynth™ architecture, enabling simultaneous generation of up to three non-integer-related frequencies. Each output supports glitchless frequency switching between two preconfigured values (F1_x/F2_x) using dedicated frequency select pins.
It operates from a single 25 MHz or 27 MHz fundamental-mode AT-cut crystal (no external load capacitors required for 6–10 pF CL), with independent core (VDD) and output (VDDO) supply rails configurable at 1.8 V, 2.5 V, or 3.3 V - supporting level translation and eliminating need for external power filtering due to high PSRR.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count | 3 independent CMOS clock outputs (CLK0–CLK2) |
| Frequency range | 2.5 kHz to 200 MHz per output; only two unique frequencies >112.5 MHz simultaneously allowed |
| Period jitter | <70 ps pk-pk (typical, all outputs active, 10-MSOP package) |
| Crystal reference | 25 MHz or 27 MHz fixed-frequency AT-cut crystal (internal 0/6/8/10 pF load capacitance) |
| Supply flexibility | VDD core: 1.71–3.6 V; VDDO per output bank: independently set to 1.8/2.5/3.3 V |
| Spread spectrum | Selectable per-output down-spread (–0.1% to –2.5%) or center-spread (±0.1% to ±1.5%) at 30–33 kHz modulation rate |
| Power consumption | 20–30 mA typical core current (3 outputs enabled); 50 µA in power-down mode |
Pinout & Package
SI5350A-B06876-GTR is packaged in a 10-pin MSOP (3.0 × 4.9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Rev. 1.2 datasheet Section 7.3 and Figure 4 (10-MSOP block diagram).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0 | Frequency Select 0 (FS_0) | Controls F1_0/F2_0 switching on CLK0; logic-high selects F2_0 |
| P1 | Frequency Select 1 (FS_1) | Controls F1_1/F2_1 switching on CLK1; logic-high selects F2_1 |
| P2 | Output Enable B (OEB_1) | Active-low enable for CLK1; high-Z when asserted |
| P3 | Output Enable A (OEB_0) | Active-low enable for CLK0; high-Z when asserted |
| P4 | Power Down (PDN) | Active-high global shutdown; reduces current to 50 µA |
| XA/XB | Crystal input | Differential crystal connection for 25/27 MHz reference; internal load caps configurable |
| CLK0–CLK2 | CMOS clock outputs | Configurable drive strength, rise/fall time, duty cycle (45–55%), and invert/non-invert |
| VDD / VDDO | Supply rails | VDD powers core logic; VDDO (shared across all outputs) sets output voltage level and swing |
Key Features
| Feature | Design Value |
|---|---|
| Factory-programmed configuration | Delivers fully validated, production-ready clock plan without I²C programming or external EEPROM |
| Dual-frequency per output | Enables dynamic clock rate switching (e.g., 74.25 MHz ↔ 74.25/1.001 MHz) via hardware pins - no firmware overhead |
| HCSL-compatible swing | Supports HCSL-level signaling (at 2.5 V VDDO) with external 511 Ω/240 Ω termination - validated for PCIe Gen 1 compliance |
| Glitchless frequency transition | Ensures zero-cycle glitches during FS-pin-triggered clock changes - critical for video/audio sync integrity |
| Independent VDD/VDDO rails | Allows interfacing with mixed-voltage SoCs (e.g., 1.8 V core + 3.3 V I/O) without level shifters |
Applications
| HDMI Audio/Video Timing | USB 2.0 Controller Clocking |
|---|---|
Use Scenario: Generating synchronized pixel clock (74.25 MHz), audio sample clock (24.576 MHz), and auxiliary timing (48 MHz) for HDMI transmitter in set-top box or Blu-ray player. IC Role / Device Role / Timing Role: Primary multi-frequency clock source replacing discrete crystals and oscillators; provides phase-aligned, low-jitter clocks to video processor, audio codec, and HDMI PHY. Use Value: Eliminates four separate timing components, reduces board area by >60%, and ensures sub-100 ps inter-clock skew for lip-sync accuracy. | Use Scenario: Supplying precise 48 MHz clock to USB 2.0 transceiver and 24.576 MHz clock to integrated audio subsystem in residential gateway or smart speaker. IC Role / Device Role / Timing Role: Single-chip clock generator delivering USB-compliant timing and audio master clock with shared crystal reference. Use Value: Achieves USB suspend/resume timing compliance and eliminates crystal-to-crystal frequency drift between USB and audio domains. |
| Ethernet PHY Synchronization | Embedded CPU Reference Clock |
Use Scenario: Providing 25 MHz reference clock to Ethernet PHY and 28.322 MHz clock to associated switch controller in network-attached storage device. IC Role / Device Role / Timing Role: Low-jitter, spread-spectrum-capable clock source meeting IEEE 802.3 EMI requirements while maintaining deterministic PHY startup timing. Use Value: Reduces radiated emissions by >6 dBµV/m at 100–300 MHz without compromising Ethernet link stability or auto-negotiation latency. | Use Scenario: Delivering 33.333 MHz system clock and 27 MHz peripheral clock to ARM Cortex-A53-based media processor in digital signage controller. IC Role / Device Role / Timing Role: Configurable, pin-selectable clock source enabling dual operating modes (e.g., performance vs. power-optimized) via FS_0/FS_1. Use Value: Enables runtime clock scaling without software intervention - reducing dynamic power by 22% in idle display mode. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5350A-B-GT | Blank (unprogrammed) version requiring ClockBuilder Pro configuration and external EEPROM; same 10-MSOP package and 3-output capability | Requires I²C host MCU for initialization; unsuitable for systems without firmware control | Select SI5350A-B06876-GTR when factory-programmed, plug-and-play operation is required with no host dependency. |
| Si5351A-B-GT | I²C-programmable (not pin-controlled); supports 3 outputs but uses different PLL architecture and lacks dual-frequency per output | Requires real-time I²C access for frequency changes; no hardware FS pin support | Choose Si5351A-B-GT only if dynamic reconfiguration via microcontroller is needed and deterministic glitchless switching is not mandatory. |
Compared with Si5350A-B-GT and Si5351A-B-GT, SI5350A-B06876-GTR delivers immediate, hardware-triggered frequency switching without firmware involvement, lower system-level jitter due to absence of I²C timing dependencies, and guaranteed factory-validated timing performance - making it optimal for cost-sensitive, firmware-light consumer electronics.
Availability
SI5350A-B06876-GTR is available at Aetrix Electronics and suitable for HDMI timing, USB controller clocking, Ethernet PHY synchronization, and embedded CPU reference applications requiring stable component supply and guaranteed factory-programmed functionality.
Supply support for SI5350A-B06876-GTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog technologies.
The Si5350A family is designed for cost-sensitive, high-volume consumer and networking applications requiring flexible, low-jitter clock generation without I²C infrastructure - targeting crystal and XO replacement in audio/video, computing, and communications equipment.
FAQ
What reference crystal is required for SI5350A-B06876-GTR?
The SI5350A-B06876-GTR requires a 25 MHz or 27 MHz fundamental-mode AT-cut crystal connected to XA/XB pins. Internal load capacitance options (0/6/8/10 pF) eliminate need for external caps in most cases; Skyworks AN551 provides full crystal selection guidance. SI5350A-B06876-GTR is factory-configured for one of these two frequencies - confirmed in its top marking and ordering code.
Does SI5350A-B06876-GTR support HCSL output levels?
Yes, SI5350A-B06876-GTR supports HCSL-compatible swing when VDDO is set to 2.5 V and appropriate external termination (511 Ω pull-up + 240 Ω pull-down) is applied per output pair. This capability is validated for PCIe Gen 1 compliance and is supported only in the 10-MSOP and 20-QFN packages - confirmed in datasheet Section 4.3 and Figure 3.
How many frequencies can SI5350A-B06876-GTR generate simultaneously above 112.5 MHz?
SI5350A-B06876-GTR can generate only two unique frequencies above 112.5 MHz at once - e.g., 125 MHz on CLK0 and 130 MHz on CLK1. Multiple outputs may replicate the same high-frequency value (e.g., 125 MHz on CLK0–CLK2), but no more than two distinct values exceeding 112.5 MHz are permitted. This constraint is specified in Table 7 Note 1 and applies identically across all Si5350A variants.
Can SI5350A-B06876-GTR be reprogrammed after deployment?
No, SI5350A-B06876-GTR is factory-programmed with a fixed configuration and contains no user-accessible nonvolatile memory. Its frequency plan, spread spectrum settings, and pin control mappings are permanently set during manufacturing. Reprogramming is not possible - unlike blank Si5350A-B-GT parts that require ClockBuilder Pro and external EEPROM.
What is the maximum allowable jitter for SI5350A-B06876-GTR in a 3-output configuration?
In the 10-MSOP package with all three outputs active, SI5350A-B06876-GTR guarantees ≤155 ps pk-pk period jitter and ≤150 ps pk-pk cycle-to-cycle jitter under worst-case conditions (Table 7). Typical performance is ≤70 ps pk-pk period jitter - measured with 74.25 MHz, 24.576 MHz, and 48 MHz outputs - and is validated across –40°C to +85°C ambient temperature.
SI5350A-B06876-GTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- -
- PLL:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Divider/Multiplier:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 10-MSOP
SI5350A-B06876-GTR FAQ
1.How can I place an order for SI5350A-B06876-GTR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5350A-B06876-GTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5350A-B06876-GTR reliable?
The price and inventory of SI5350A-B06876-GTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5350A-B06876-GTR is usually 5 days.
3.What payment methods are accepted for SI5350A-B06876-GTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5350A-B06876-GTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5350A-B06876-GTR?
SI5350A-B06876-GTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5350A-B06876-GTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5350A-B06876-GTR?
For technical support, including SI5350A-B06876-GTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5350A-B06876-GTR requirements.
6.How does Aetrix verify that SI5350A-B06876-GTR is sourced from the original manufacturer or authorized distributors?
All SI5350A-B06876-GTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5350A-B06876-GTR meets industry standards.
7.What is the process for return or replacement of SI5350A-B06876-GTR?
All SI5350A-B06876-GTR units undergo pre-shipment inspection (PSI). If there is an issue with SI5350A-B06876-GTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5350A-B06876-GTR part is unused and in its original packaging.
Return procedure for SI5350A-B06876-GTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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