Skyworks Solutions Inc. SI5350A-B06878-GM
- Part No.:
- SI5350A-B06878-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- 20-VFQFN Exposed Pad
- Datasheet:
-
SI5350A-B06878-GM.pdf
- Description:
- IC ANY FREQ ANY OUT XTAL 20QFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,535
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Product details
Overview
SI5350A-B06878-GM from Skyworks Solutions is a factory-programmed, pin-controlled CMOS clock generator delivering up to 8 independent output frequencies (2.5 kHz–200 MHz) with 0 ppm synthesis error, <70 ps pk-pk period jitter, and configurable spread spectrum on any output. It replaces multiple crystals/XOs in audio/video processors, HDMI interfaces, and Ethernet PHYs using a single 25 or 27 MHz crystal reference.
For engineers reviewing the SI5350A-B06878-GM datasheet, SI5350A-B06878-GM pinout, SI5350A-B06878-GM application, or SI5350A-B06878-GM equivalent, key selection factors include its 20-QFN package with 20-pin layout, dual-PLL + fractional MultiSynth architecture, per-output VDDO voltage scaling (1.8/2.5/3.3 V), and support for glitchless frequency switching via FS_0/FS_1 pins.
Technical Context
The SI5350A-B06878-GM implements two high-frequency PLLs (PLLA and PLLB) feeding eight independent fractional MultiSynth dividers - enabling simultaneous non-integer-related outputs. PLLA supports spread spectrum modulation (±0.1% to ±1.5%, 31.5 kHz rate); PLLB does not.
It accepts only a fixed 25 or 27 MHz crystal (XA/XB), not external clock inputs. Output clocks CLK0–CLK7 are fully configurable for frequency, rise/fall time, duty cycle (45–55% below 160 MHz), inversion, and disable state (high/low/Hi-Z), with separate VDDO pins enabling mixed-voltage signaling across output banks.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count | 8 independent CMOS clock outputs (CLK0–CLK7) |
| Frequency range | 2.5 kHz to 200 MHz per output; max two unique frequencies >112.5 MHz simultaneously |
| Period jitter | <70 ps pk-pk (typical, all outputs active, worst-case real-world plan) |
| Core supply | 1.71–1.89 V / 2.25–2.75 V / 3.0–3.6 V; independent of output supplies |
| Output supply (VDDOx) | 1.71–1.89 V / 2.25–2.75 V / 3.0–3.6 V per bank; enables level translation |
| Reference input | 25 MHz or 27 MHz fundamental-mode AT-cut crystal only (no CLKIN support) |
| Spread spectrum | Selectable per-output down-spread (–0.1% to –2.5%) or center-spread (±0.1% to ±1.5%) |
Pinout & Package
SI5350A-B06878-GM is packaged in a 20-pin QFN (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Rev. 1.2 datasheet Section 7.1 and Figure 4 (20-QFN block diagram).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| XA, XB | Crystal oscillator input pair | Differential crystal connection; internal load capacitance selectable (0/6/8/10 pF) via ClockBuilder Pro |
| CLK0–CLK7 | CMOS clock outputs | Eight independent outputs; each configurable for frequency, invert/non-invert, drive strength, and disable state |
| VDDOA–VDDOD | Output buffer supply rails | Four independent VDDO pins (each powers two CLK outputs); enable mixed-voltage signaling (e.g., 1.8 V + 3.3 V) |
| VDD | Core logic supply | Supplies PLLs, control logic, and MultiSynths; must be powered before or concurrently with all VDDO pins |
| GND | Ground reference | Four dedicated ground pins (P2, P3, P4, GND) plus thermal pad; critical for jitter and EMI performance |
| P0–P4 | Configurable control inputs | Programmable as OEB_0/1/2 (output enable), PDN (power-down), FS_0/FS_1 (dual-frequency select), or SSEN (spread spectrum enable) |
Key Features
| Feature | Design Value |
|---|---|
| Factory-programmed configuration | Preloaded with exact frequency plan (SI5350A-B06878-GM); no I²C required for operation |
| Glitchless frequency switching | F1_x/F2_x dual-frequency mode on CLK0–CLK2 enabled by FS_0/FS_1 pins; zero-cycle transition |
| HCSL-compatible outputs | Configurable when VDDO = 2.5 V + external 511 Ω/240 Ω termination; supported only in 10-MSOP and 20-QFN packages |
| Per-output spread spectrum | Independent enable/disable per CLK output driven by PLLA; reduces EMI without affecting PLLB-synchronized clocks |
| Low-power operation | 25 mA typical core current (8 outputs enabled); 50 µA power-down current with PDN = high |
| PSRR robustness | Eliminates need for external LDO filtering; maintains jitter performance under noisy supply conditions |
Applications
| HDMI Audio/Video Timing | Ethernet PHY Clocking |
|---|---|
Use Scenario: Generating synchronized clocks for HDMI transmitter (74.25 MHz), audio codec (24.576 MHz), and video processor (27 MHz) in set-top boxes. IC Role / Device Role / Timing Role: Single-chip replacement for three discrete crystals/XOs; provides phase-aligned, low-jitter clocks with shared crystal reference. Use Value: Reduces BOM cost and board area vs. multiple oscillators; eliminates inter-clock skew and improves signal integrity in high-speed video paths. |
Use Scenario: Supplying 125 MHz reference to Ethernet PHY and 25 MHz to MAC controller in residential gateways. IC Role / Device Role / Timing Role: Primary clock source for IEEE 802.3-compliant physical layer; supports spread spectrum to meet FCC Class B radiated emissions limits. Use Value: Enables EMI reduction without compromising timing margin; avoids costly shielding or PCB rework during compliance testing. |
| USB 2.0 + PCIe Gen1 System Clock | Multi-Standard Video Encoder |
Use Scenario: Delivering 48 MHz to USB 2.0 transceiver and 100 MHz (PCIe Gen1 compliant) to bridge controller in embedded servers. IC Role / Device Role / Timing Role: Dual-frequency clock generator with glitchless switching between USB and PCIe modes via FS_0 pin. Use Value: Eliminates need for separate clock sources and multiplexing logic; ensures seamless mode transitions without system reset. |
Use Scenario: Providing 33.333 MHz (CPU), 28.322 MHz (SDRAM), and 22.5792 MHz (HDTV encoder) in DVD/Blu-ray players. IC Role / Device Role / Timing Role: Multi-synthesizer generating non-integer-related frequencies from one crystal; supports static phase offset for video pipeline alignment. Use Value: Synchronizes disparate video subsystems without external delay lines; simplifies timing closure in multi-clock-domain SoCs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5351A-B-GM | I²C-programmable (not factory-configured); 8 outputs; requires external EEPROM or host MCU for initialization | Suitable for prototyping or field-upgradable systems; lacks pin-control features (FS_0/FS_1, SSEN) | Choose Si5351A-B-GM if dynamic reconfiguration is needed; SI5350A-B06878-GM is preferred for fixed, production-ready timing plans. |
| CDCE906PWR | TI 6-output LVCMOS clock generator; single PLL + integer dividers; max 230 MHz output; no spread spectrum | Limited to integer-related frequencies; higher typical jitter (>100 ps pk-pk); no per-output VDDO scaling | Choose CDCE906PWR only for cost-sensitive, low-channel-count designs where frequency flexibility and jitter are secondary. |
Compared with Si5351A-B-GM and CDCE906PWR, SI5350A-B06878-GM delivers superior frequency agility (0 ppm non-integer synthesis), lower jitter, and hardware-based control - making it optimal for volume production of audio/video and networking equipment requiring deterministic, low-risk timing.
Availability
SI5350A-B06878-GM is available at Aetrix Electronics and suitable for HDMI transceivers, Ethernet PHYs, USB 2.0 controllers, and multi-standard video encoders requiring stable component supply, guaranteed factory programming, and long-term lifecycle support.
Supply support for SI5350A-B06878-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with emphasis on performance, integration, and reliability.
The Si5350A-B product line delivers factory-programmed, pin-configurable clock generators targeting cost-sensitive consumer and networking applications where crystal/XO replacement, EMI reduction, and board-space savings are critical design goals.
FAQ
What reference crystal is required for SI5350A-B06878-GM?
The SI5350A-B06878-GM requires a 25 MHz or 27 MHz fundamental-mode AT-cut crystal connected to XA/XB pins. It does not accept external clock signals. Internal load capacitance (0/6/8/10 pF) is configurable via ClockBuilder Pro; crystals requiring 12 pF load use 10 pF internal + ≤2 pF external capacitance.
Does SI5350A-B06878-GM support HCSL output levels?
Yes, SI5350A-B06878-GM supports HCSL-compatible swing when VDDO for the relevant output pair is set to 2.5 V and external 511 Ω/240 Ω termination is applied. This feature is validated only for the 10-MSOP and 20-QFN packages - not the 16-QFN variant.
How many frequencies can SI5350A-B06878-GM generate above 112.5 MHz simultaneously?
SI5350A-B06878-GM can output only two unique frequencies above 112.5 MHz at once (e.g., 125 MHz and 130 MHz). Multiple copies of the same high-frequency signal (e.g., 125 MHz on four outputs) are permitted, but three distinct frequencies >112.5 MHz violate device architecture constraints.
What is the power-down current of SI5350A-B06878-GM?
When the PDN pin is driven high, SI5350A-B06878-GM enters full power-down mode with a maximum supply current of 50 µA. All outputs are disabled, PLLs halted, and internal logic powered down - enabling ultra-low standby power in battery-backed or energy-conscious systems.
Can SI5350A-B06878-GM generate different frequencies on CLK0 and CLK1 using the same FS pin?
Yes - SI5350A-B06878-GM allows linking FS_0 or FS_1 to multiple outputs (e.g., CLK0 and CLK1) so both switch frequencies synchronously. This is confirmed in the functional description (Section 5) and Figure 8 of the datasheet, enabling coordinated clock domain transitions in multi-processor systems.
SI5350A-B06878-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 20-VFQFN Exposed Pad
- Packaging:
- Strip
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- -
- PLL:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Divider/Multiplier:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 20-QFN (4x4)
SI5350A-B06878-GM FAQ
1.How can I place an order for SI5350A-B06878-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5350A-B06878-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5350A-B06878-GM reliable?
The price and inventory of SI5350A-B06878-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5350A-B06878-GM is usually 5 days.
3.What payment methods are accepted for SI5350A-B06878-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5350A-B06878-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5350A-B06878-GM?
SI5350A-B06878-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5350A-B06878-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5350A-B06878-GM?
For technical support, including SI5350A-B06878-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5350A-B06878-GM requirements.
6.How does Aetrix verify that SI5350A-B06878-GM is sourced from the original manufacturer or authorized distributors?
All SI5350A-B06878-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5350A-B06878-GM meets industry standards.
7.What is the process for return or replacement of SI5350A-B06878-GM?
All SI5350A-B06878-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5350A-B06878-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5350A-B06878-GM part is unused and in its original packaging.
Return procedure for SI5350A-B06878-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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