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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5350A-B07052-GM

Name: SI5350A-B07052-GM
Brand: Skyworks Solutions Inc.
SKU: SI5350A-B07052-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5350A-B07052-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 20-VFQFN Exposed Pad

Datasheet:: SI5350A-B07052-GM.pdf

Description:: IC ANY FREQ ANY OUT XTAL 20QFN

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Product details

Overview

SI5350A-B07052-GM from Skyworks Solutions is a factory-programmed, pin-controlled CMOS clock generator delivering up to 8 independent output frequencies (2.5 kHz–200 MHz) with 0 ppm synthesis error, low period jitter (<70 ps pk-pk), and configurable spread spectrum on any output. It replaces multiple crystals/XOs in audio/video systems, residential gateways, and networking equipment using a single 25 or 27 MHz crystal reference.

For engineers reviewing the SI5350A-B07052-GM datasheet, SI5350A-B07052-GM pinout, SI5350A-B07052-GM application, or SI5350A-B07052-GM equivalent, key selection considerations include its 20-QFN package with 8 outputs, dual-PLL + fractional MultiSynth architecture, independent VDD/VDDO voltage rails (1.8/2.5/3.3 V), and support for glitchless frequency switching via FS_0/FS_1 pins.

Technical Context

The SI5350A-B07052-GM implements two high-frequency PLLs (PLLA and PLLB) feeding eight independent fractional MultiSynth dividers-one per output-enabling simultaneous non-integer-related frequencies. PLLA supports spread spectrum modulation (±0.1% to ±1.5% center-spread, 30–33 kHz rate); PLLB does not.

It accepts only a fixed 25 or 27 MHz crystal on XA/XB inputs, with internal load capacitance options (0/6/8/10 pF). Output drive strength is configurable per VDDO rail, supporting HCSL-compatible swing (2.5 V VDDO + external termination) on 10-MSOP and 20-QFN packages only.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	8 independent CMOS clock outputs (CLK0–CLK7)
Frequency range	2.5 kHz to 200 MHz per output; max two unique frequencies >112.5 MHz simultaneously
Period jitter	<70 ps pk-pk (typical, all outputs active, worst-case config)
Core supply	1.71–1.89 V, 2.25–2.75 V, or 3.0–3.6 V - supports mixed-voltage system integration
Output supply	VDDOx independently set per output bank (1.71–1.89 V / 2.25–2.75 V / 3.0–3.6 V)
Crystal reference	25 MHz or 27 MHz fundamental-mode AT-cut crystal only (no CLKIN support)
Spread spectrum	Selectable per-output down-spread (–0.1% to –2.5%) or center-spread (±0.1% to ±1.5%)

Pinout & Package

SI5350A-B07052-GM is packaged in a 20-pin QFN (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.2 datasheet Section 7.1.

Pin/Terminal	Circuit Role	Design Meaning
XA, XB	Crytal input pair	Differential crystal oscillator interface; requires 25 or 27 MHz AT-cut crystal; internal load caps configurable
CLK0–CLK7	CMOS clock outputs	Eight independent buffered clocks; each supports invert/non-invert, enable/disable, and frequency select (F1_x/F2_x)
VDD	Core supply	Powers PLLs, logic, and MultiSynths; must ramp before or with VDDOx
VDDOA–VDDOD	Output buffer supplies	Four independent VDDO rails (VDDOA for CLK0/1, VDDOB for CLK2/3, etc.); enable level translation and HCSL compatibility
P0–P4	Configurable control pins	Programmable as OEB_0/1/2 (output enables), PDN (power-down), FS_0/FS_1 (frequency select), or SSEN (spread spectrum enable)
GND	Ground reference	Common return for core and output buffers; thermal pad must be soldered to PCB ground plane

Key Features

Feature	Design Value
Factory-programmed configuration	Preloaded with exact frequency plan (SI5350A-B07052-GM), eliminating I²C programming during system boot
Glitchless frequency switching	F1_x/F2_x dual-frequency mode on CLK0–CLK2 enables zero-cycle transition between rates using FS_0/FS_1 pins
Independent VDD/VDDO rails	Allows core logic at 1.8 V while driving 3.3 V or 2.5 V system clocks - eliminates level shifters
HCSL-compatible outputs	When VDDOA = 2.5 V and CLK0/CLK1 are inverted relative to each other, meets HCSL jitter and swing requirements with external 511 Ω/240 Ω termination
Low-power operation	25 mA typical core current with all 8 outputs enabled; 50 µA power-down current when PDN = high

Applications

Audio/Video Processing	Residential Gateway
Use Scenario: HDMI transmitter, audio codec, and video processor require synchronized but non-integer-related clocks (e.g., 74.25 MHz, 24.576 MHz, 48 MHz). IC Role / Device Role / Timing Role: Single-chip clock source replacing three discrete crystals/XOs; provides exact frequencies with 0 ppm error and <70 ps jitter. Use Value: Reduces BOM count, board space, and EMI by consolidating timing sources while maintaining signal integrity across high-speed interfaces.	Use Scenario: Dual-band Wi-Fi router integrating CPU, Ethernet PHY, USB controller, and PCIe switch - each requiring distinct clock domains. IC Role / Device Role / Timing Role: Centralized clock generator delivering 33.33 MHz (CPU), 125 MHz (PCIe), 25 MHz (USB), and 28.322 MHz (Ethernet) from one device. Use Value: Eliminates timing skew between subsystems and simplifies layout by removing multiple crystal placements and associated load capacitors.
Networking Equipment	Set-Top Box
Use Scenario: 10/25G Ethernet line card needing precise, low-jitter clocks for SERDES lanes and management MCU. IC Role / Device Role / Timing Role: Generates 156.25 MHz (SERDES reference), 25 MHz (management bus), and spread-spectrum 100 MHz (EMI reduction) on dedicated outputs. Use Value: Meets PCIe Gen1 jitter compliance and reduces radiated emissions without external filtering or shielding modifications.	Use Scenario: HD broadcast receiver decoding MPEG-TS streams, driving HDMI, SPDIF, and tuner IF sections with distinct sample rates. IC Role / Device Role / Timing Role: Supplies 27 MHz (tuner), 22.5792 MHz (SPDIF), 74.25 MHz (HDMI), and 48 MHz (audio DSP) - all derived from one 27 MHz crystal. Use Value: Ensures sample-rate accuracy across audio/video paths, preventing lip-sync errors and buffer underruns in real-time playback.

Audio/Video Processing

Residential Gateway

Use Scenario: HDMI transmitter, audio codec, and video processor require synchronized but non-integer-related clocks (e.g., 74.25 MHz, 24.576 MHz, 48 MHz).

IC Role / Device Role / Timing Role: Single-chip clock source replacing three discrete crystals/XOs; provides exact frequencies with 0 ppm error and <70 ps jitter.

Use Value: Reduces BOM count, board space, and EMI by consolidating timing sources while maintaining signal integrity across high-speed interfaces.

Use Scenario: Dual-band Wi-Fi router integrating CPU, Ethernet PHY, USB controller, and PCIe switch - each requiring distinct clock domains.

IC Role / Device Role / Timing Role: Centralized clock generator delivering 33.33 MHz (CPU), 125 MHz (PCIe), 25 MHz (USB), and 28.322 MHz (Ethernet) from one device.

Use Value: Eliminates timing skew between subsystems and simplifies layout by removing multiple crystal placements and associated load capacitors.

Networking Equipment

Set-Top Box

Use Scenario: 10/25G Ethernet line card needing precise, low-jitter clocks for SERDES lanes and management MCU.

IC Role / Device Role / Timing Role: Generates 156.25 MHz (SERDES reference), 25 MHz (management bus), and spread-spectrum 100 MHz (EMI reduction) on dedicated outputs.

Use Value: Meets PCIe Gen1 jitter compliance and reduces radiated emissions without external filtering or shielding modifications.

Use Scenario: HD broadcast receiver decoding MPEG-TS streams, driving HDMI, SPDIF, and tuner IF sections with distinct sample rates.

IC Role / Device Role / Timing Role: Supplies 27 MHz (tuner), 22.5792 MHz (SPDIF), 74.25 MHz (HDMI), and 48 MHz (audio DSP) - all derived from one 27 MHz crystal.

Use Value: Ensures sample-rate accuracy across audio/video paths, preventing lip-sync errors and buffer underruns in real-time playback.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5350A-B-GM	Same 20-QFN package and 8-output capability, but blank/unprogrammed - requires ClockBuilder Pro configuration and I²C programming in-system	No factory-loaded frequency plan; unsuitable for boot-critical or I²C-less designs	Select SI5350A-B-GM only if dynamic reconfiguration or field-upgradable clock plans are required
Si5351A-B-GM	I²C-programmable 8-output variant with identical architecture but supports XTAL-only reference only (no voltage/CLKIN option); higher typical jitter (95 ps pk-pk)	Lacks pin-control features (FS_0/FS_1, SSEN, PDN); requires microcontroller firmware support	Choose Si5351A-B-GM when design includes an I²C master and flexibility to change frequencies post-deployment is needed

Compared with SI5350A-B-GM and Si5351A-B-GM, SI5350A-B07052-GM delivers guaranteed boot-time clock availability without host intervention, deterministic pin-controlled frequency switching, and lower jitter - making it optimal for cost-sensitive, high-reliability embedded timing where configuration stability is critical.

Availability

SI5350A-B07052-GM is available at Aetrix Electronics and suitable for audio/video processing, residential gateway, and networking equipment requiring stable component supply, long-term lifecycle support, and factory-verified timing performance.

Supply support for SI5350A-B07052-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5350A product line delivers factory-programmable, low-jitter clock generation for cost-sensitive applications replacing multiple crystals and oscillators - targeting consumer electronics, networking, and embedded systems where timing consolidation and EMI reduction are critical.

FAQ

What reference crystal is required for SI5350A-B07052-GM?

The SI5350A-B07052-GM requires a 25 MHz or 27 MHz fundamental-mode AT-cut crystal connected to XA/XB pins. It does not accept external clock signals (CLKIN) or voltage-controlled references. Crystal load capacitance must be 6–12 pF; internal load caps (0/6/8/10 pF) are configurable via ClockBuilder Pro, and external caps ≤2 pF may be added if needed. SI5350A-B07052-GM is preconfigured for a specific crystal frequency per its part number suffix.

Does SI5350A-B07052-GM support HCSL output levels?

Yes, SI5350A-B07052-GM supports HCSL-compatible swing on CLK0/CLK1, CLK2/CLK3, CLK4/CLK5, or CLK6/CLK7 pairs when the corresponding VDDO rail is set to 2.5 V and one clock in the pair is inverted. This requires external 511 Ω pull-down and 240 Ω series termination per output, as specified in Figure 3 of the datasheet. HCSL mode is only supported in the 20-QFN and 10-MSOP packages - not in the 16-QFN variant.

How many frequencies can SI5350A-B07052-GM generate above 112.5 MHz simultaneously?

SI5350A-B07052-GM can output no more than two *unique* frequencies above 112.5 MHz at the same time. For example, 125 MHz on CLK0 and 130 MHz on CLK1 is allowed; adding 150 MHz on CLK2 violates the limit. However, duplicate frequencies are permitted - e.g., 125 MHz on CLK0–CLK3 and 130 MHz on CLK4–CLK7 satisfies the constraint. This limitation arises from internal PLL resource allocation and is documented in Table 7, Note 1.

Can SI5350A-B07052-GM be reprogrammed after manufacturing?

No, SI5350A-B07052-GM is factory-programmed with a fixed configuration and cannot be reprogrammed. Its frequency plan, spread spectrum settings, output inversions, and control pin mappings are permanently stored in on-chip memory during manufacturing. Unlike blank variants (e.g., SI5350A-B-GM), SI5350A-B07052-GM has no I²C interface enabled and lacks runtime programmability - ensuring deterministic timing behavior from power-on reset.

What is the maximum allowable junction temperature for SI5350A-B07052-GM in continuous operation?

The absolute maximum junction temperature for SI5350A-B07052-GM is 150 °C, per Table 13. For reliable continuous operation, the device must remain within its recommended operating range (–40 °C to +85 °C ambient), with junction temperature calculated using θJA = 41 °C/W (20-QFN, 4-layer board). At 85 °C ambient and 25 mA core current, junction temperature stays well below 150 °C - confirming safe thermal operation under typical conditions. SI5350A-B07052-GM includes thermal shutdown protection.

SI5350A-B07052-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 20-VFQFN Exposed Pad

Packaging:: Strip

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 20-QFN (4x4)

SI5350A-B07052-GM FAQ

1.How can I place an order for SI5350A-B07052-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5350A-B07052-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5350A-B07052-GM reliable?

The price and inventory of SI5350A-B07052-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5350A-B07052-GM is usually 5 days.

3.What payment methods are accepted for SI5350A-B07052-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5350A-B07052-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5350A-B07052-GM?

SI5350A-B07052-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5350A-B07052-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5350A-B07052-GM?

For technical support, including SI5350A-B07052-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5350A-B07052-GM requirements.

6.How does Aetrix verify that SI5350A-B07052-GM is sourced from the original manufacturer or authorized distributors?

All SI5350A-B07052-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5350A-B07052-GM meets industry standards.

7.What is the process for return or replacement of SI5350A-B07052-GM?

All SI5350A-B07052-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5350A-B07052-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5350A-B07052-GM part is unused and in its original packaging.

Return procedure for SI5350A-B07052-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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