Skyworks Solutions Inc. SI5350C-B03054-GT

Overview

SI5350C-B03054-GT from Skyworks Solutions is a factory-programmed, pin-controlled CMOS clock generator with dual PLL + MultiSynth fractional synthesis architecture, delivering up to 3 free-running or synchronized output clocks (CLK0–CLK2) in the 2.5 kHz–200 MHz range, with <70 ps pk-pk period jitter, 0 ppm frequency error, and support for spread spectrum on PLLA-referenced outputs. It operates from a 25 or 27 MHz crystal or external 10–100 MHz CLKIN reference and targets compact timing consolidation in audio/video and networking edge devices.

For engineers reviewing the SI5350C-B03054-GT datasheet, SI5350C-B03054-GT pinout, SI5350C-B03054-GT application, or SI5350C-B03054-GT equivalent, key selection considerations include its 10-pin MSOP package, 3-output configuration, factory-programmed frequency plan, independent VDD/VDDO voltage scaling (1.8/2.5/3.3 V), and pin-based control of output enable (OEB_0/1/2), power down (PDN), and frequency select (FS_0/1).

Technical Context

The SI5350C-B03054-GT implements a dual-loop PLL architecture: PLLA accepts either the internal crystal oscillator (25/27 MHz) or external CLKIN (10–100 MHz), while PLLB is crystal-only. Each of its three outputs (CLK0–CLK2) is driven by an independent MultiSynth fractional divider, enabling non-integer-related frequencies with exact synthesis and glitchless switching between two preconfigured frequencies per output via FS_0/FS_1 pins.

It supports configurable output drive strength (50 Ω typical), rise/fall time control, static phase offset, HCSL-compatible swing (with 2.5 V VDDO and external termination), and spread spectrum modulation (±0.1% to ±1.5% center-spread or –0.1% to –2.5% down-spread at 30–33 kHz) exclusively on PLLA-referenced outputs - not on PLLB-synchronized clocks.

Key Specifications

Pinout & Package

SI5350C-B03054-GT is housed in a 10-pin MSOP package (3.0 × 4.9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are electrically validated per Skyworks Rev. 1.2 datasheet Section 7.3 and Figure 4 (10-MSOP block diagram).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5350A-B-GT and Si5351A-B-GT, the SI5350C-B03054-GT uniquely supports both crystal and external CLKIN references in a factory-programmed, pin-controlled form factor - enabling plug-and-play timing with zero firmware dependency and lowest jitter among the three for fixed-function deployments.

Availability

SI5350C-B03054-GT is available at Aetrix Electronics and suitable for audio/video equipment, residential gateways, and printer/scanner applications requiring stable component supply, long-term lifecycle assurance, and guaranteed factory-programmed configurations.

Supply support for SI5350C-B03054-GT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for infrastructure, automotive, and consumer markets.

The Si5350C-B product line delivers factory-programmed, pin-configurable clock generators optimized for timing consolidation in space-constrained, cost-sensitive embedded systems where flexibility, low jitter, and zero-software integration are critical.

FAQ

What reference sources does the SI5350C-B03054-GT support?

The SI5350C-B03054-GT supports two reference sources: a 25 MHz or 27 MHz fundamental-mode AT-cut crystal connected to XA/XB pins, or an external single-ended clock signal (10–100 MHz) applied to the CLKIN pin. It cannot use both simultaneously for different outputs - the crystal feeds PLLB (free-running), while CLKIN feeds PLLA (synchronous). The SI5350C-B03054-GT configuration is factory-programmed to use one or the other per output path.

How many frequencies can the SI5350C-B03054-GT generate simultaneously above 112.5 MHz?

The SI5350C-B03054-GT can generate no more than two unique frequencies above 112.5 MHz at once - for example, 125 MHz on CLK0 and 130 MHz on CLK1 is valid, but adding 150 MHz on CLK2 violates the specification. However, duplicate frequencies above 112.5 MHz are permitted: 125 MHz may be assigned to all three outputs (CLK0–CLK2) simultaneously. This constraint is enforced by the MultiSynth fractional divider architecture in the SI5350C-B03054-GT.

Does the SI5350C-B03054-GT support HCSL output levels?

Yes, the SI5350C-B03054-GT supports HCSL-compatible swing on CLK0/CLK1 when VDDOA is set to 2.5 V and the INV function is enabled on one output of the pair. This requires external 511 Ω and 240 Ω resistors per output as shown in Figure 3 of the datasheet. HCSL mode is only supported in the 10-MSOP package (i.e., SI5350C-B03054-GT), not in QFN variants - a key electrical capability confirmed for this specific part number.

What is the power-down current of the SI5350C-B03054-GT?

The SI5350C-B03054-GT draws ≤50 µA in power-down mode when the PDN pin is driven high. This state disables all PLLs, stops all clock outputs, and powers down internal regulators and logic blocks while retaining factory-programmed configuration. The 50 µA value is a maximum guarantee across –40°C to +85°C ambient and all supply voltages, as specified in Table 4 of the Skyworks datasheet for the SI5350C-B03054-GT.

Can the SI5350C-B03054-GT generate spread spectrum on all three outputs?

Spread spectrum is available only on outputs referenced to PLLA - i.e., those using CLKIN as their source. Outputs derived from the crystal oscillator (PLLB) cannot have spread spectrum enabled. Since the SI5350C-B03054-GT's factory-programmed configuration determines which outputs map to which PLL, spread spectrum capability depends on that assignment. It is not universally available across all three outputs unless all are PLLA-referenced - a constraint inherent to the SI5350C-B03054-GT architecture.