Skyworks Solutions Inc. SI5350C-B04473-GTR
- Part No.:
- SI5350C-B04473-GTR
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
SI5350C-B04473-GTR.pdf
- Description:
- IC ANY FREQ ANY OUT REF C 10MSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5350C-B04473-GTR from Skyworks Solutions is a factory-programmed, pin-controlled CMOS clock generator with dual PLL + MultiSynth fractional synthesis architecture. It delivers up to 4 independent, non-integer-related output frequencies from 2.5 kHz to 200 MHz, supports 0 ppm frequency error, <70 ps pk-pk period jitter (typ), and operates from a 25 or 27 MHz crystal reference. It serves as a drop-in replacement for multiple XOs and PLLs in compact networking and audio/video timing systems.
For engineers reviewing the SI5350C-B04473-GTR datasheet, SI5350C-B04473-GTR pinout, SI5350C-B04473-GTR application, or SI5350C-B04473-GTR equivalent, key selection considerations include its 4-output 16-QFN package, pin-configurable spread spectrum per output, glitchless frequency switching via FS_0/FS_1, HCSL-compatible swing support at 2.5 V VDDO, and factory-programmed configuration eliminating I²C programming overhead.
Technical Context
The SI5350C-B04473-GTR implements a dual-loop PLL architecture: PLLA drives outputs requiring spread spectrum or high-precision synthesis, while PLLB supports synchronous clocks referenced to CLKIN. Each of its four outputs (CLK0–CLK3) is assigned to an independent MultiSynth divider with programmable F1_x/F2_x frequency pairs selectable via FS_0/FS_1 pins.
It accepts either a 25 MHz or 27 MHz fundamental-mode AT-cut crystal (XA/XB) or an external 10–100 MHz clock on CLKIN. Core supply (VDD) and output buffer supplies (VDDOA–VDDOD) are independently configurable at 1.8 V, 2.5 V, or 3.3 V, enabling level translation and mixed-voltage system interfacing without external level shifters.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count | 4 independent CMOS clock outputs (CLK0–CLK3), each configurable with two frequencies (F1_x/F2_x) |
| Frequency range | 2.5 kHz to 200 MHz per output; only two unique frequencies >112.5 MHz allowed simultaneously |
| Period jitter | <70 ps pk-pk (typ), measured across 10k cycles with default 50 Ω drive strength |
| Reference input | 25 MHz or 27 MHz crystal (XA/XB) or 10–100 MHz external clock (CLKIN) |
| Supply flexibility | VDD core: 1.71–3.6 V; VDDO outputs: independently set to 1.71–3.6 V per bank (VDDOA–VDDOD) |
| Spread spectrum | Selectable per output (down-spread: –0.1% to –2.5%; center-spread: ±0.1% to ±1.5%) at 30–33 kHz modulation rate |
| Power consumption | 21 mA typ (4 outputs enabled); 50 µA max in power-down mode (PDN = VDD) |
Pinout & Package
SI5350C-B04473-GTR is packaged in a 3×3 mm, 16-pin QFN (RoHS-compliant, exposed thermal pad). Pin functions are defined per Skyworks Rev. 1.2 datasheet Section 7.2.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD | Core supply | 1.71–3.6 V digital core power; must be powered before or concurrently with all VDDO pins |
| VDDOA | Output supply A | Supplies CLK0/CLK1; sets output voltage level (1.8/2.5/3.3 V) and enables HCSL compatibility at 2.5 V |
| VDDOB | Output supply B | Supplies CLK2/CLK3; independent voltage setting allows mixed-swing outputs on same device |
| GND | Ground | Common reference for core and all output buffers; connects to exposed thermal pad |
| CLK0–CLK3 | CMOS clock outputs | Configurable rise/fall time, duty cycle (45–55%), and invert/non-invert; each supports glitchless F1_x/F2_x switching |
| XA / XB | Crystal inputs | Differential crystal oscillator interface; supports 25 MHz or 27 MHz AT-cut crystals with internal 0/6/8/10 pF load capacitance |
| CLKIN | External reference input | Accepts 10–100 MHz single-ended clock; used for synchronous outputs locked to external source |
| P0–P3 | Programmable control pins | Configurable as SSEN (spread spectrum enable), PDN (power down), FS_0/FS_1 (frequency select), or OEB_0/OEB_1 (output enable) |
Key Features
| Feature | Design Value |
|---|---|
| Dual PLL + MultiSynth synthesis | Enables simultaneous generation of up to 4 non-integer-related frequencies with 0 ppm error relative to reference |
| Glitchless frequency switching | F1_x/F2_x switching on CLK0–CLK2 via FS_0/FS_1 pins eliminates clock interruptions during runtime reconfiguration |
| HCSL-compatible outputs | When VDDOA or VDDOB = 2.5 V, CLK0/CLK1 or CLK2/CLK3 can be configured with 50 Ω output impedance and appropriate swing for HCSL receivers |
| Independent VDDO banks | VDDOA and VDDOB allow separate voltage assignment for each output pair-critical for interfacing with mixed-voltage SoCs or FPGAs |
| Factory-programmed configuration | SI5350C-B04473-GTR ships preconfigured via ClockBuilder Pro; no I²C bus, firmware, or runtime programming required |
Applications
| Networking PHY Timing | Audio/Video Clock Synthesis |
|---|---|
Use Scenario: Providing synchronized clocks to Ethernet PHY, USB controller, and HDMI port in residential gateway or SOHO router. IC Role / Device Role / Timing Role: Primary clock generator delivering 25 MHz (PHY), 48 MHz (USB), 74.25 MHz (HDMI), and 125 MHz (switch fabric) from single 27 MHz crystal. Use Value: Replaces four discrete XOs, reduces board area by >60%, eliminates inter-clock skew, and enables shared spread spectrum for EMI reduction across all domains. |
Use Scenario: Generating precise sample-rate clocks for audio codec, video processor, and display interface in Blu-ray player or set-top box. IC Role / Device Role / Timing Role: Free-running clock source producing 24.576 MHz (audio), 27 MHz (video), 28.322 MHz (HDCP), and 33.333 MHz (system bus) with sub-ppm accuracy. Use Value: Eliminates crystal proliferation, ensures phase-coherent multi-domain timing, and supports dynamic sample-rate switching via FS_0/FS_1 without clock glitches. |
| Print/Scan Engine Control | Industrial Embedded Instrumentation |
Use Scenario: Driving stepper motor controllers, image sensor interfaces, and USB host in multifunction printer or document scanner. IC Role / Device Role / Timing Role: Configured with 48 MHz (USB), 74.25 MHz (image sensor), 125 MHz (FPGA logic), and 28.322 MHz (motor encoder) outputs. Use Value: Enables deterministic real-time motion control and image capture synchronization while reducing BOM cost and layout complexity versus discrete oscillators. |
Use Scenario: Supplying stable, low-jitter clocks to ADC/DAC, FPGA, and microcontroller in handheld test equipment or portable oscilloscope. IC Role / Device Role / Timing Role: Generates 100 MHz (ADC sampling), 50 MHz (FPGA fabric), 25 MHz (MCU), and 48 MHz (USB) from internal 25 MHz crystal. Use Value: Meets stringent jitter requirements for 12+ bit ADCs (<70 ps pk-pk), supports battery-powered operation via 21 mA typical current draw, and simplifies thermal design with 103 °C/W θJA (16-QFN). |
Equivalent & Alternatives
The following parts are listed as comparable options for similar clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5350A-B-GM1 | 3-output variant in 10-MSOP; supports only XTAL reference (no CLKIN); no HCSL support | Limited to 3 clocks and single-reference designs; unsuitable for multi-domain sync or HCSL interfaces | Choose only if design requires exactly 3 outputs, uses only crystal reference, and operates at ≤100 MHz. |
| Si5351C-B-GM1 | I²C-programmable 4-output version; supports XTAL + CLKIN reference; higher jitter (95 ps pk-pk typ) | Requires I²C host and runtime configuration; better for field-upgradable or multi-config systems | Select when flexible post-production frequency changes are needed, and added MCU overhead is acceptable. |
Compared with Si5350A-B-GM1 and Si5351C-B-GM1, SI5350C-B04473-GTR offers factory-programmed simplicity, CLKIN+XTAL dual-reference capability, and lowest jitter-making it optimal for fixed-function, space-constrained, and EMI-sensitive embedded timing applications.
Availability
SI5350C-B04473-GTR is available at Aetrix Electronics and suitable for networking PHY timing, audio/video clock synthesis, print/scan engine control, and industrial embedded instrumentation requiring stable component supply, guaranteed factory programming, and long-term production continuity.
Supply support for SI5350C-B04473-GTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with emphasis on performance, integration, and reliability.
The Si5350C family is designed for high-density, low-power clock generation in space-constrained consumer, networking, and industrial systems-replacing multiple discrete timing components with a single, factory-configured, pin-controlled solution.
FAQ
What reference sources does the SI5350C-B04473-GTR support?
The SI5350C-B04473-GTR supports two reference sources: a 25 MHz or 27 MHz fundamental-mode AT-cut crystal connected to XA/XB pins, or an external 10–100 MHz clock applied to the CLKIN pin. It cannot use both simultaneously for different outputs-the reference choice is fixed per factory configuration. The SI5350C-B04473-GTR is preprogrammed to use one of these references, and that setting is immutable after shipment.
Does the SI5350C-B04473-GTR support HCSL output levels?
Yes, the SI5350C-B04473-GTR supports HCSL-compatible outputs when VDDOA or VDDOB is set to 2.5 V and the corresponding output pair (CLK0/CLK1 or CLK2/CLK3) is configured with 50 Ω output impedance and inverted complementary signaling. This functionality is validated for the 16-QFN package and requires external 511 Ω and 240 Ω termination resistors per HCSL standard. The SI5350C-B04473-GTR's factory configuration includes this HCSL setup where applicable.
How many unique frequencies above 112.5 MHz can the SI5350C-B04473-GTR generate simultaneously?
The SI5350C-B04473-GTR can generate only two unique frequencies above 112.5 MHz at the same time-for example, 125 MHz on CLK0 and 130 MHz on CLK1. Additional outputs above 112.5 MHz must duplicate one of those two frequencies (e.g., CLK2 = 125 MHz, CLK3 = 130 MHz). This limitation is inherent to the MultiSynth divider architecture and applies regardless of whether frequencies are free-running or synchronized. The SI5350C-B04473-GTR's factory programming adheres strictly to this constraint.
Can the SI5350C-B04473-GTR perform glitchless frequency switching?
Yes, the SI5350C-B04473-GTR supports glitchless frequency switching on CLK0–CLK2 using the FS_0 and FS_1 pins. Each of those outputs is preconfigured with two frequencies (F1_x and F2_x); asserting FS_0 or FS_1 selects between them without clock interruption or metastability. This feature is enabled in the SI5350C-B04473-GTR's factory programming and requires no external logic beyond pull-up/pull-down resistors on the FS pins.
What is the typical power consumption of the SI5350C-B04473-GTR?
The SI5350C-B04473-GTR draws 21 mA typical current when all four outputs are enabled and operating under nominal conditions (VDD = 2.5 V, TA = 25 °C). Power drops to ≤50 µA in power-down mode (PDN = VDD). Unused outputs can be individually disabled to further reduce current-each active output contributes ~2.2–5.6 mA to IDDOx depending on load and frequency. The SI5350C-B04473-GTR's low-power design makes it suitable for thermally constrained or battery-assisted applications.
SI5350C-B04473-GTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- -
- PLL:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Divider/Multiplier:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 10-MSOP
SI5350C-B04473-GTR FAQ
1.How can I place an order for SI5350C-B04473-GTR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5350C-B04473-GTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5350C-B04473-GTR reliable?
The price and inventory of SI5350C-B04473-GTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5350C-B04473-GTR is usually 5 days.
3.What payment methods are accepted for SI5350C-B04473-GTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5350C-B04473-GTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5350C-B04473-GTR?
SI5350C-B04473-GTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5350C-B04473-GTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5350C-B04473-GTR?
For technical support, including SI5350C-B04473-GTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5350C-B04473-GTR requirements.
6.How does Aetrix verify that SI5350C-B04473-GTR is sourced from the original manufacturer or authorized distributors?
All SI5350C-B04473-GTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5350C-B04473-GTR meets industry standards.
7.What is the process for return or replacement of SI5350C-B04473-GTR?
All SI5350C-B04473-GTR units undergo pre-shipment inspection (PSI). If there is an issue with SI5350C-B04473-GTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5350C-B04473-GTR part is unused and in its original packaging.
Return procedure for SI5350C-B04473-GTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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