Skyworks Solutions Inc. SI5350C-B04585-GTR

Overview

SI5350C-B04585-GTR from Skyworks Solutions is a factory-programmed, pin-controlled CMOS clock generator with dual PLL + MultiSynth fractional synthesis architecture. It delivers up to 4 independent, non-integer-related output frequencies (2.5 kHz–200 MHz) with 0 ppm frequency error, <70 ps pk-pk period jitter (typ), and configurable spread spectrum-used in networking, audio/video, and residential gateway timing systems.

For engineers reviewing the SI5350C-B04585-GTR datasheet, SI5350C-B04585-GTR pinout, SI5350C-B04585-GTR application, or SI5350C-B04585-GTR equivalent, this device supports glitchless frequency switching via FS_0/FS_1 pins, HCSL-compatible outputs at 2.5 V VDDO, and operation from 25/27 MHz crystal or 10–100 MHz CLKIN reference-critical for PCIe Gen 1-compliant multi-clock domain designs.

Technical Context

The SI5350C-B04585-GTR implements a dual-loop PLL architecture: PLLA drives outputs requiring spread spectrum (down/center spread selectable per output), while PLLB serves synchronous clocks locked to CLKIN. Each of its four outputs (CLK0–CLK3) maps to an independent MultiSynth fractional divider enabling exact frequency synthesis without integer constraints.

It accepts dual reference inputs-25/27 MHz crystal across XA/XB or external 10–100 MHz clock on CLKIN-and supports static phase offset, rise/fall time control, and per-output voltage translation via separate VDDOA/VDDOB supply pins (1.8/2.5/3.3 V). Power-down (PDN), output enable (OEB_0/1/2), and spread spectrum enable (SSEN) are implemented as dedicated programmable control pins (P0–P3).

Key Specifications

Pinout & Package

SI5350C-B04585-GTR is housed in a 16-pin QFN (3 mm × 3 mm, 0.5 mm pitch) package with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.2 datasheet Section 7.2 and Figure 4 (16-QFN block diagram).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with SI5350C-B04585-GTR, Si5350A-B-GM1 offers lower channel count and no spread spectrum-reducing flexibility in EMI-sensitive multi-clock systems-while Si5351C-B-GM1 trades factory-set reliability for field configurability, increasing firmware complexity but enabling dynamic frequency updates.

Availability

SI5350C-B04585-GTR is available at Aetrix Electronics and suitable for networking switches, audio/video equipment, residential gateways, and PCIe Gen 1-compliant embedded systems requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5350C-B04585-GTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs.

The SI5350C-B04585-GTR belongs to Skyworks' Si5350 family of factory-programmable clock generators designed to replace multiple crystals, oscillators, and PLLs in space-constrained, cost-sensitive consumer and networking applications.

FAQ

What reference sources does the SI5350C-B04585-GTR support?

The SI5350C-B04585-GTR supports two reference sources: a 25 MHz or 27 MHz crystal connected across XA/XB pins, or an external 10–100 MHz clock applied to the CLKIN pin. It cannot use both simultaneously for different outputs-the design must select one primary reference source during factory programming. The SI5350C-B04585-GTR does not support voltage-controlled references or I²C reconfiguration post-deployment.

How many unique frequencies above 112.5 MHz can the SI5350C-B04585-GTR generate simultaneously?

The SI5350C-B04585-GTR supports only two unique frequencies above 112.5 MHz across all four outputs. For example, it can deliver 125 MHz on CLK0 and 130 MHz on CLK1-but adding 150 MHz on CLK2 violates the specification. However, duplicate frequencies (e.g., 125 MHz on CLK0–CLK3) are permitted. This constraint is enforced by the MultiSynth fractional divider architecture and verified in Skyworks Table 7.

Does the SI5350C-B04585-GTR support HCSL-compatible outputs, and what is required?

Yes, the SI5350C-B04585-GTR supports HCSL-compatible outputs when VDDOA or VDDOB is set to 2.5 V and the INV function is enabled on one clock of a pair (e.g., CLK0 and CLK1). External 511 Ω and 240 Ω resistors must be added per Figure 3 in the datasheet. This capability is limited to the 10-MSOP and 20-QFN packages; the 16-QFN package (SI5350C-B04585-GTR) supports it per Skyworks Rev. 1.2 Section 4.3.

What is the power-down current and recovery time for the SI5350C-B04585-GTR?

In power-down mode (PDN = VDD), the SI5350C-B04585-GTR draws ≤50 µA. Recovery to valid clock output takes ≤10 ms (TRDY) after VDD reaches minimum operating voltage, assuming CL = 5 pF and fCLKn > 1 MHz. If PLL bypass mode is configured, recovery shortens to ≤1 ms (TBYP). These values are guaranteed across –40°C to +85°C per Skyworks Table 5.

Can the SI5350C-B04585-GTR generate spread spectrum on all four outputs?

Spread spectrum is supported only on outputs referenced to PLLA-not PLLB. Since SI5350C-B04585-GTR allows per-output PLL selection, spread spectrum can be enabled on any subset of CLK0–CLK3, provided those outputs are assigned to PLLA during factory configuration via ClockBuilder Pro. Outputs locked to CLKIN (PLLB) cannot have spread spectrum applied.