Skyworks Solutions Inc. SI5350C-B06051-GTR

Overview

SI5350C-B06051-GTR from Skyworks Solutions is a factory-programmed, pin-controlled CMOS clock generator with dual PLL + MultiSynth fractional synthesis architecture. It delivers up to 4 independent, non-integer-related output frequencies from 2.5 kHz to 200 MHz, supports 0 ppm frequency error, <70 ps pk-pk period jitter (typ), and operates from a 25 or 27 MHz crystal reference. It serves as a drop-in replacement for multiple crystals, XOs, and discrete PLLs in compact timing-critical systems like residential gateways and audio/video equipment.

For engineers reviewing the SI5350C-B06051-GTR datasheet, SI5350C-B06051-GTR pinout, SI5350C-B06051-GTR application, or SI5350C-B06051-GTR equivalent, key selection considerations include its 4-output 16-QFN (3×3 mm) package, configurable spread spectrum per output, glitchless frequency switching via FS pins, HCSL-compatible swing at 2.5 V VDDO, and support for both free-running and CLKIN-synchronized clocks.

Technical Context

The SI5350C-B06051-GTR implements a dual-loop PLL architecture with eight independent MultiSynth fractional dividers - four of which are active in this 4-output variant. Each output (CLK0–CLK3) can be assigned to either PLLA or PLLB, enabling mixed synchronous/free-running operation with static phase offset control.

It accepts reference inputs from either an internal 25/27 MHz crystal (XA/XB) or external 10–100 MHz clock (CLKIN), and features programmable control pins (P0–P3) for spread spectrum enable (SSEN), power down (PDN), and dual-frequency selection (FS0/FS1) on outputs CLK0–CLK2. Output buffers support independent VDDO voltage rails (1.8/2.5/3.3 V) and rise/fall time control.

Key Specifications

Pinout & Package

SI5350C-B06051-GTR is housed in a 16-pin QFN (3 × 3 mm) package with exposed thermal pad. Pin functions align with the Si5350C-B family's standardized 16-QFN layout per Skyworks datasheet Rev. 1.2, Section 7.2.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with SI5350C-B06051-GTR, Si5350A-B-GM1 offers lower pin count but sacrifices CLKIN flexibility and one output; Si5351C-B-GM1 trades factory optimization for I²C configurability - making it better suited for prototyping or adaptive systems where clock plans evolve post-deployment.

Availability

SI5350C-B06051-GTR is available at Aetrix Electronics and suitable for residential gateways, audio/video equipment, and network-attached storage requiring stable component supply, long-term lifecycle assurance, and guaranteed factory-programmed configurations.

Supply support for SI5350C-B06051-GTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and consumer markets.

The Si5350C-B product line delivers factory-programmed, pin-configurable clock generators targeting space-constrained, cost-sensitive applications where replacing multiple discrete timing components with a single IC improves reliability and simplifies design.

FAQ

What reference sources does the SI5350C-B06051-GTR support?

The SI5350C-B06051-GTR supports two reference sources: a 25 MHz or 27 MHz fundamental-mode AT-cut crystal connected to XA/XB pins, or a single-ended 10–100 MHz external clock applied to the CLKIN pin. It cannot use both simultaneously for different outputs - all outputs derive from either the crystal oscillator or CLKIN, selected per MultiSynth configuration in ClockBuilder Pro.

Does the SI5350C-B06051-GTR support HCSL output levels?

Yes, the SI5350C-B06051-GTR supports HCSL-compatible swing when VDDOA or VDDOB is set to 2.5 V and the INV function is enabled on one clock of a pair (e.g., CLK0 and CLK1). This generates a differential HCSL signal with 50 Ω output impedance, but only in the 10-MSOP and 20-QFN packages - not the 16-QFN variant of SI5350C-B06051-GTR.

How many unique high-frequency outputs can the SI5350C-B06051-GTR generate above 112.5 MHz?

The SI5350C-B06051-GTR can generate no more than two unique frequencies above 112.5 MHz simultaneously. For example, it may output 125 MHz on CLK0 and 130 MHz on CLK1, but adding a third distinct frequency such as 150 MHz on CLK2 violates the specification. Duplicate frequencies (e.g., 125 MHz on CLK0–CLK3) are permitted.

What is the power-up behavior of the SI5350C-B06051-GTR?

The SI5350C-B06051-GTR achieves valid output clocks within 2 ms (typ) after VDD reaches minimum operating voltage, assuming CL = 5 pF and fCLKn > 1 MHz. In PLL bypass mode - where outputs are directly derived from the crystal or CLKIN without PLL multiplication - power-up time reduces to 0.5 ms (typ), enabling faster system boot in timing-critical applications.

Can the SI5350C-B06051-GTR generate spread spectrum on all four outputs?

Spread spectrum is supported only on outputs referenced to PLLA, not PLLB. Since SI5350C-B06051-GTR's 4-output configuration assigns CLK0–CLK1 to PLLA and CLK2–CLK3 to PLLB (per functional block diagram), only CLK0 and CLK1 can be configured with spread spectrum. Enabling it on CLK2 or CLK3 has no effect - the feature is disabled for PLLB-sourced outputs.