Skyworks Solutions Inc. SI5350C-B06463-GTR

Overview

SI5350C-B06463-GTR from Skyworks Solutions is a factory-programmed, pin-controlled CMOS clock generator with dual PLL + MultiSynth fractional synthesis architecture. It delivers up to 4 independent, non-integer-related output frequencies (2.5 kHz–200 MHz) with 0 ppm frequency error, <70 ps pk-pk period jitter (typ), and configurable spread spectrum per output - used in networking equipment, audio/video systems, and PCIe Gen 1-compliant timing subsystems.

For engineers reviewing the SI5350C-B06463-GTR datasheet, SI5350C-B06463-GTR pinout, SI5350C-B06463-GTR application, or SI5350C-B06463-GTR equivalent, key selection considerations include its 16-QFN (3×3 mm) package, support for 25/27 MHz crystal or 10–100 MHz CLKIN reference, independent VDD/VDDO voltage scaling (1.8/2.5/3.3 V), and pin-configurable control logic (FS_0/1, SSEN, PDN, OEB_0/1/2).

Technical Context

The SI5350C-B06463-GTR implements a dual-loop PLL architecture where PLLA and PLLB each drive dedicated MultiSynth fractional dividers, enabling simultaneous free-running (crystal-referenced) and synchronized (CLKIN-referenced) outputs. Each of its four outputs (CLK0–CLK3) supports independent frequency selection, spread spectrum (PLLA only), and invert/non-invert configuration.

It accepts either a 25 MHz or 27 MHz fundamental-mode AT-cut crystal (XA/XB) or an external 10–100 MHz clock on CLKIN. Core supply (VDD) and output buffer supplies (VDDOA–VDDOD) operate independently at 1.8 V, 2.5 V, or 3.3 V, with PSRR optimized to eliminate external filtering. Power-down (PDN) and output-enable (OEB) pins provide deterministic state control.

Key Specifications

Pinout & Package

SI5350C-B06463-GTR is housed in a 16-pin QFN package (3 mm × 3 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.2 datasheet Section 7.2 and Figure 4 (16-QFN block diagram).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with SI5350C-B06463-GTR, Si5350A-B-GM1 lacks CLKIN capability and reduces output count to three, making it unfit for hybrid reference architectures; Si5350C-B-GM adds four more outputs in a larger package but retains identical jitter, frequency range, and control pin functionality - ideal for scalable timing subsystems.

Availability

SI5350C-B06463-GTR is available at Aetrix Electronics and suitable for networking equipment, audio/video systems, and printer/scanner timing applications requiring stable component supply, long-term lifecycle support, and factory-programmed consistency.

Supply support for SI5350C-B06463-GTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog products.

The Si5350C family is designed for high-density, multi-frequency clock generation in space-constrained consumer, enterprise, and industrial systems - replacing discrete oscillators and PLLs with a single programmable device.

FAQ

What reference sources does SI5350C-B06463-GTR support?

SI5350C-B06463-GTR supports either a 25 MHz or 27 MHz fundamental-mode AT-cut crystal connected to XA/XB pins, or a single-ended 10–100 MHz clock applied to the CLKIN pin. It cannot accept both simultaneously for different PLLs - the reference source is selected at factory programming. The device does not support I²C reconfiguration after shipment.

How many unique frequencies above 112.5 MHz can SI5350C-B06463-GTR generate simultaneously?

SI5350C-B06463-GTR can output no more than two distinct frequencies above 112.5 MHz at once - for example, 125 MHz on CLK0 and 130 MHz on CLK1 is valid, but adding 150 MHz on CLK2 violates the specification. Multiple copies of the same high-frequency signal (e.g., 125 MHz on all four outputs) are permitted.

Does SI5350C-B06463-GTR support HCSL output levels?

Yes - SI5350C-B06463-GTR supports HCSL-compatible swing when the corresponding VDDO rail (e.g., VDDOA for CLK0/CLK1) is set to 2.5 V and external 511 Ω/240 Ω termination is applied per output pair. This capability is confirmed for the 16-QFN package and requires inversion of one clock in the pair to form a differential signal.

What is the power consumption of SI5350C-B06463-GTR with all four outputs active?

With all four outputs enabled and operating under typical conditions (VDD = 2.5 V, TA = 25 °C), SI5350C-B06463-GTR draws 21 mA (typ) from the core VDD supply, as specified in Table 4 of the Skyworks datasheet Rev. 1.2. Output buffer current is additional and scales per loaded output (2.2–5.6 mA per CLKx at CL = 5 pF).

Can SI5350C-B06463-GTR perform glitchless frequency switching?

Yes - SI5350C-B06463-GTR supports hardware-based glitchless frequency switching on CLK0–CLK2 using the factory-configured FS_0 and FS_1 pins. Each of those outputs can be programmed with two distinct frequencies (F1_x/F2_x), and transition between them occurs without clock interruption or metastability, as verified in functional testing per Skyworks Application Note AN551.