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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5351A-A-GMR

Name: SI5351A-A-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5351A-A-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5351A-A-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 20-VFQFN Exposed Pad

Datasheet:: SI5351A-A-GMR.pdf

Description:: IC CLOCK GENERATOR 20QFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5351A-A-GMR from Silicon Labs is an I²C-programmable, 8-output CMOS clock generator with internal oscillator (no VCXO), generating free-running frequencies from 8 kHz to 160 MHz per output with 0 ppm synthesis error. It replaces crystals, crystal oscillators, and fanout buffers in cost-sensitive embedded timing applications using a single 25 or 27 MHz AT-cut crystal reference. Designed for multi-clock-domain systems, it supports independent frequency, phase offset, and spread spectrum on each output.

For engineers reviewing the SI5351A-A-GMR datasheet, SI5351A-A-GMR pinout, SI5351A-A-GMR application, or SI5351A-A-GMR equivalent, key selection criteria include its 8-output QFN/QSOP package options, I²C-configurable MultiSynth fractional dividers, 100 ps pk-pk period jitter, separate VDDO voltage rails (1.8/2.5/3.3 V), and support for glitchless frequency changes and static phase offset.

Technical Context

The SI5351A-A-GMR implements a dual-PLL architecture (PLLA and PLLB) fed by an internal 25 or 27 MHz crystal oscillator - no external CLKIN or VC input required. Each PLL drives up to eight independent high-resolution MultiSynth fractional dividers, enabling non-integer-related output frequencies across all eight channels.

Its output stage includes per-bank VDDO supply pins (VDDOA–VDDOD), programmable rise/fall time control (0.5–1.5 ns), configurable output states (hi-Z, stop-high, stop-low), and optional spread spectrum (down or center spread, 0.1–2.5%) on PLLA-referenced outputs only. The device lacks VCXO functionality and CLKIN synchronization capability - distinguishing it from Si5351B/C variants.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	8 independent CMOS clock outputs (QFN/QSOP packages); 3 outputs in MSOP variant
Frequency range	8 kHz to 160 MHz per output; exact synthesis with 0 ppm error via MultiSynth dividers
Period jitter	35–100 ps pk-pk (typ. 35 ps); enables low-noise timing for HDMI, USB, and Ethernet PHYs
Supply voltages	Core VDD: 2.25–2.75 V or 3.0–3.6 V; Output VDDO: 1.71–1.89 V / 2.25–2.75 V / 3.0–3.6 V (per bank)
Crystal reference	25 or 27 MHz fixed-frequency AT-cut crystal; internal load caps (6/8/10 pF) eliminate external components
I²C interface	7-bit slave address (0x60 or 0x61 via A0 pin); Standard/Fast Mode (100/400 kbps); burst writes with auto-increment
Power consumption	22–35 mA (3 outputs enabled), 27–45 mA (8 outputs enabled); 20 µA in power-down mode

Pinout & Package

SI5351A-A-GMR is packaged in a 20-pin QFN (4×4 mm, 0.5 mm pitch) with wettable flanks, optimized for thermal performance (θ_JA = 51 °C/W) and space-constrained PCB layouts. Pin functions are validated per Silicon Labs' official Si5351A Pin Descriptions (20-Pin QFN) document section 9.

Pin/Terminal	Circuit Role	Design Meaning
XA, XB	Crytal oscillator inputs	Accept 25 or 27 MHz AT-cut crystal; internal load capacitance eliminates need for external caps
VDD, GND	Core power and ground	VDD supports 2.25–2.75 V or 3.0–3.6 V; requires local 0.1 µF + 10 µF decoupling per datasheet Section 6.1
VDDOA–VDDOD	Output buffer supplies	Four independent 1.8/2.5/3.3 V rails - one per 2-output bank - enabling mixed-voltage system interfacing
SCL, SDA, A0	I²C interface and address select	7-bit slave address 0x60 (A0=GND) or 0x61 (A0=VDD); pull-ups required per I²C spec (4.7 kΩ typical)
OEB	Output enable (active-low)	Glitchless enable/disable; outputs enter user-configurable state (hi-Z, stop-high, or stop-low) when high
CLK0–CLK7	CMOS clock outputs	Each supports independent frequency, phase offset, spread spectrum, and polarity inversion via register config

Key Features

Feature	Design Value
MultiSynth fractional synthesis	Enables any frequency from 8 kHz to 160 MHz per output with zero ppm error - eliminates need for multiple crystals
Per-output spread spectrum	Configurable down-spread (–0.1% to –2.5%) or center-spread (±0.1% to ±1.5%) reduces EMI without hardware changes
Static phase offset control	333 ps/step resolution allows precise inter-output timing alignment for DDR, video, or multi-lane serial interfaces
Independent output voltage rails	VDDOA–VDDOD allow simultaneous 1.8 V, 2.5 V, and 3.3 V CMOS outputs - simplifies level-shifting in mixed-voltage SoC designs
Glitchless frequency switching	Hardware-managed transitions ensure no runt pulses or metastability during dynamic reconfiguration over I²C

Applications

HDMI Audio/Video Timing	USB 2.0 Host Controller Clocking
Use Scenario: Generating synchronized 24.576 MHz audio, 27 MHz pixel, and 74.25 MHz TMDS clocks for HDMI transmitters and receivers. IC Role / Device Role / Timing Role: Primary multi-frequency clock source replacing discrete crystals and oscillators across audio, video, and data lanes. Use Value: Eliminates 3+ discrete timing components while maintaining <100 ps jitter and exact frequency ratios required for AV sync compliance.	Use Scenario: Providing 48 MHz USB PHY clock and 12 MHz USB controller reference in set-top boxes or media hubs. IC Role / Device Role / Timing Role: Single-chip clock generator delivering both high-accuracy USB timing domains with independent jitter specs. Use Value: Reduces BOM count and layout area vs. dual-crystal solution; supports USB suspend/resume via I²C-controlled output enable (OEB).
Network Attached Storage (NAS) Controller	Industrial PLC Communication Module
Use Scenario: Supplying 125 MHz Ethernet PHY clock, 100 MHz PCIe Gen1 reference, and 25 MHz SATA controller clock in compact NAS enclosures. IC Role / Device Role / Timing Role: PCIe Gen1-compliant clock source with deterministic phase relationship between Ethernet and storage clocks. Use Value: Meets PCIe Gen1 jitter spec (100 ps pk-pk) while enabling shared crystal reference - lowers cost vs. dedicated oscillators.	Use Scenario: Delivering 16.384 MHz RS-485 transceiver clock, 1.024 MHz CAN FD baud rate generator, and 32.768 kHz RTC reference in DIN-rail PLC modules. IC Role / Device Role / Timing Role: Precision multi-rate timing engine supporting legacy and modern industrial protocols from one footprint. Use Value: Enables protocol coexistence without clock domain crossing issues; 8 kHz–160 MHz range covers all common industrial baud rates and timers.

HDMI Audio/Video Timing

USB 2.0 Host Controller Clocking

Use Scenario: Generating synchronized 24.576 MHz audio, 27 MHz pixel, and 74.25 MHz TMDS clocks for HDMI transmitters and receivers.

IC Role / Device Role / Timing Role: Primary multi-frequency clock source replacing discrete crystals and oscillators across audio, video, and data lanes.

Use Value: Eliminates 3+ discrete timing components while maintaining <100 ps jitter and exact frequency ratios required for AV sync compliance.

Use Scenario: Providing 48 MHz USB PHY clock and 12 MHz USB controller reference in set-top boxes or media hubs.

IC Role / Device Role / Timing Role: Single-chip clock generator delivering both high-accuracy USB timing domains with independent jitter specs.

Use Value: Reduces BOM count and layout area vs. dual-crystal solution; supports USB suspend/resume via I²C-controlled output enable (OEB).

Network Attached Storage (NAS) Controller

Industrial PLC Communication Module

Use Scenario: Supplying 125 MHz Ethernet PHY clock, 100 MHz PCIe Gen1 reference, and 25 MHz SATA controller clock in compact NAS enclosures.

IC Role / Device Role / Timing Role: PCIe Gen1-compliant clock source with deterministic phase relationship between Ethernet and storage clocks.

Use Value: Meets PCIe Gen1 jitter spec (100 ps pk-pk) while enabling shared crystal reference - lowers cost vs. dedicated oscillators.

Use Scenario: Delivering 16.384 MHz RS-485 transceiver clock, 1.024 MHz CAN FD baud rate generator, and 32.768 kHz RTC reference in DIN-rail PLC modules.

IC Role / Device Role / Timing Role: Precision multi-rate timing engine supporting legacy and modern industrial protocols from one footprint.

Use Value: Enables protocol coexistence without clock domain crossing issues; 8 kHz–160 MHz range covers all common industrial baud rates and timers.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5351B-A-GMR	Includes integrated VCXO; supports voltage-controlled tuning (±30 to ±240 ppm) and external CLKIN reference	Required where synchronous clock locking or frequency pulling (e.g., video genlock, jitter cleaning) is needed	Select SI5351A-A-GMR only if free-running clocks suffice; Si5351B-A-GMR adds VCXO complexity and cost
CDCE906PWR	6-output, 0.1–230 MHz; uses external crystal + PLL; no fractional synthesis; higher typical jitter (150 ps pk-pk)	Limited to simpler multi-clock systems without stringent jitter or exact-ratio requirements	Choose CDCE906PWR for legacy TI-based designs or where I²C configurability is secondary to analog PLL familiarity

Compared with Si5351B-A-GMR and CDCE906PWR, the SI5351A-A-GMR delivers superior frequency flexibility (0 ppm error, 8 kHz–160 MHz) and lower jitter in free-running applications, while avoiding VCXO calibration overhead and analog PLL design constraints.

Availability

SI5351A-A-GMR is available at Aetrix Electronics and suitable for HDMI timing, USB host controllers, network-attached storage, industrial PLCs, and residential gateways requiring stable component supply and long-term production continuity.

Supply support for SI5351A-A-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Labs is a fabless semiconductor company specializing in precision timing, wireless, and MCU solutions, with deep expertise in clock synthesis and RF integration.

The Si5351 family was designed specifically to replace discrete timing components in cost-sensitive, space-constrained consumer and industrial electronics - emphasizing programmability, low jitter, and minimal external BOM.

FAQ

What is the maximum output frequency supported by the SI5351A-A-GMR?

The SI5351A-A-GMR supports a maximum output frequency of 160 MHz per channel, verified across all eight outputs in QFN/QSOP packages. This limit applies regardless of configuration method (I²C register write or ClockBuilder Desktop), and is guaranteed under recommended operating conditions (VDD = 2.5 V or 3.3 V, TA = –40 to 85 °C). Frequencies above 160 MHz are not supported and may result in undefined behavior.

Does the SI5351A-A-GMR require an external crystal, and what specifications must it meet?

Yes, the SI5351A-A-GMR requires a 25 or 27 MHz fundamental-mode AT-cut crystal connected to XA/XB pins. Per Silicon Labs' specification, the crystal must have load capacitance of 6–12 pF, ESR ≤ 150 Ω, and drive level ≤ 100 µW. Internal load capacitors (6/8/10 pF) eliminate need for external caps unless CL = 12 pF - then add 2 pF external.

Can the SI5351A-A-GMR generate different output voltages simultaneously?

Yes. The SI5351A-A-GMR provides four independent output supply pins - VDDOA, VDDOB, VDDOC, and VDDOD - each configurable for 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous generation of mixed-voltage CMOS clocks (e.g., 1.8 V for FPGA I/O banks and 3.3 V for legacy microcontrollers) without external level shifters.

Is spread spectrum supported on all outputs of the SI5351A-A-GMR?

No. Spread spectrum is only available on outputs referenced to PLLA (CLK0–CLK3 and CLK4–CLK7 depending on crosspoint routing), not on PLLB-referenced outputs. The SI5351A-A-GMR supports down-spread (–0.1% to –2.5%) or center-spread (±0.1% to ±1.5%) modulation at 30–33 kHz, reducing EMI without affecting timing accuracy of non-SSC outputs.

How does the SI5351A-A-GMR handle power-up and output enable sequencing?

The SI5351A-A-GMR powers up with outputs disabled (OEB = high) and loads default configuration from OTP memory. Outputs activate glitchlessly upon OEB transition to low, beginning on the next valid clock edge. Power-up time is 1–10 ms (typ. 1 ms) from VDD reaching minimum, and output enable time is ≤10 µs - ensuring clean startup in processor-boot-critical systems.

SI5351A-A-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 20-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

Type:: Clock Generator

PLL:: Yes

Input:: Crystal

Output:: LVCMOS

Number of Circuits:: 1

Ratio - Input:Output:: 1:8

Differential - Input:Output:: No/No

Frequency - Max:: 200MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 3.6V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 20-QFN (4x4)

SI5351A-A-GMR FAQ

1.How can I place an order for SI5351A-A-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5351A-A-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5351A-A-GMR reliable?

The price and inventory of SI5351A-A-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5351A-A-GMR is usually 5 days.

3.What payment methods are accepted for SI5351A-A-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5351A-A-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5351A-A-GMR?

SI5351A-A-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5351A-A-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5351A-A-GMR?

For technical support, including SI5351A-A-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5351A-A-GMR requirements.

6.How does Aetrix verify that SI5351A-A-GMR is sourced from the original manufacturer or authorized distributors?

All SI5351A-A-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5351A-A-GMR meets industry standards.

7.What is the process for return or replacement of SI5351A-A-GMR?

All SI5351A-A-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5351A-A-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5351A-A-GMR part is unused and in its original packaging.

Return procedure for SI5351A-A-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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