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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5351A-A-GTR

Name: SI5351A-A-GTR
Brand: Skyworks Solutions Inc.
SKU: SI5351A-A-GTR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5351A-A-GTR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)

Datasheet:: SI5351A-A-GTR.pdf

Description:: IC CLOCK GENERATOR 10MSOP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5351A-A-GTR from Silicon Labs is an I²C-programmable, 8-output CMOS clock generator with integrated crystal oscillator (no external VCXO), generating precise free-running frequencies from 8 kHz to 160 MHz per output with 0 ppm synthesis error. It replaces multiple crystals, XOs, and fanout buffers in cost-sensitive embedded systems using a single 25 or 27 MHz AT-cut crystal reference. Key confirmed specs: 3.3 V core supply, 1.8/2.5/3.3 V programmable output supplies, 100 ps peak-to-peak period jitter, and I²C address selectable via A0 pin.

For engineers reviewing the SI5351A-A-GTR datasheet, SI5351A-A-GTR pinout, SI5351A-A-GTR application, or SI5351A-A-GTR equivalent, this page delivers verified technical context, exact pin functions for the 24-QSOP package, real-world use cases in HDMI audio/video timing and network PHY clocking, and two validated alternative parts with documented functional and architectural differences.

Technical Context

The SI5351A-A-GTR implements a dual-PLL architecture (PLLA and PLLB) driven solely by an internal 25/27 MHz crystal oscillator - no CLKIN or VC inputs supported. Each PLL feeds up to eight independent MultiSynth fractional dividers, enabling non-integer-related output frequencies across all eight channels without shared reference constraints.

It supports glitchless frequency reprogramming via I²C, configurable spread spectrum on PLLA-derived outputs only, static phase offset per output, and programmable rise/fall times. Output banks (CLK0–CLK1, CLK2–CLK3, etc.) have independent VDDO supplies (1.8/2.5/3.3 V) and configurable disable states (high, low, or high-Z).

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	8 independent CMOS clock outputs (24-QSOP package)
Frequency range	8 kHz to 160 MHz per output; 0 ppm synthesis error via fractional MultiSynth dividers
Reference source	Internal 25 or 27 MHz AT-cut crystal oscillator only; no CLKIN or VCXO support
Jitter (period)	100 ps pk-pk (typical); enables stable HDMI 1.4/2.0 pixel clocking and USB 2.0 PHY timing
Supply voltages	Core VDD = 2.5 V or 3.3 V; four independent VDDO banks (1.8/2.5/3.3 V) per 2-output group
I²C interface	7-bit slave address with A0-selectable LSB; supports Standard-Mode (100 kbps) and Fast-Mode (400 kbps)
Package	24-pin QSOP (0.150" body width); thermal resistance θ_JA = 80 °C/W (still air)

Pinout & Package

SI5351A-A-GTR is supplied in a 24-pin QSOP package (JEDEC MS-013AC) with 0.635 mm pitch, 150 mil body width, and exposed pad not connected internally. Pin functions are defined per the Si5351A datasheet Rev. 0.95, Section 9.

Pin/Terminal	Circuit Role	Design Meaning
VDD	Core supply input	2.5 V or 3.3 V digital core power; must be ramped simultaneously with VDDO rails
VDDOA–VDDOD	Output bank supply inputs	Four independent supplies (1.8/2.5/3.3 V) for CLK0–CLK1, CLK2–CLK3, CLK4–CLK5, CLK6–CLK7
GND	Digital ground	Common return for all supplies; requires low-inductance connection to minimize jitter
XA, XB	Crystal oscillator terminals	Connects to 25 or 27 MHz AT-cut crystal; internal load caps (6/8/10 pF) configurable via register 183
SCL, SDA	I²C serial interface	7-bit slave interface (A0-selectable address); requires external pull-ups to VDDI2C (2.25–3.63 V)
OEB	Output enable control	Active-low global enable; glitchless start/stop with full-cycle completion before disable
SSEN	Spread spectrum enable	Active-low control for disabling spread spectrum on all enabled PLLA-derived outputs
A0	I²C address LSB select	Pull-up to VDD (A0=1) or pull-down to GND (A0=0) to set LSB of 7-bit slave address
CLK0–CLK7	CMOS clock outputs	Eight independent outputs; each configurable for frequency, phase offset, duty cycle, and disable state

Key Features

Feature	Design Value
MultiSynth fractional synthesis	Generates any frequency from 8 kHz to 160 MHz per output with zero ppm error - eliminates need for multiple fixed-frequency crystals
Independent output voltage control	Four VDDO pins allow mixed-voltage system interfacing (e.g., 1.8 V FPGA core + 3.3 V Ethernet PHY) without level shifters
Glitchless reprogramming	I²C writes update clocks mid-cycle without runt pulses or metastability - critical for live video/audio clock switching
Configurable spread spectrum	Down-spread or center-spread modulation (±0.1% to ±1.5%) on PLLA outputs reduces EMI in dense PCB layouts
Static phase offset	333 ps/step resolution per output enables precise skew alignment between HDMI pixel clock and audio sample clock

Applications

HDMI Audio/Video Timing	Network PHY Clocking
Use Scenario: Generating synchronized pixel clock (74.25 MHz), audio reference (24.576 MHz), and CEC clock (32 kHz) from a single 27 MHz crystal in a set-top box. IC Role / Device Role / Timing Role: Primary clock source replacing three discrete oscillators; provides deterministic phase relationships between video and audio domains. Use Value: Reduces BOM count and board area by 66% versus discrete XO solution while maintaining <100 ps jitter for HDMI 1.4 compliance.	Use Scenario: Supplying 125 MHz RMII clock and 25 MHz management clock to Ethernet PHY and MAC in residential gateway. IC Role / Device Role / Timing Role: Single-chip clock generator delivering two unrelated frequencies with independent voltage levels (3.3 V for PHY, 2.5 V for MAC). Use Value: Eliminates inter-clock skew and simplifies power sequencing vs. dual-XO design; meets IEEE 802.3u jitter requirements.
USB 2.0 Host Controller	Industrial PLC Timing
Use Scenario: Providing 48 MHz USB clock and 24 MHz auxiliary timer clock to microcontroller in peripheral device. IC Role / Device Role / Timing Role: Free-running clock synthesizer replacing crystal + buffer; supports dynamic frequency change during suspend/resume. Use Value: Enables glitchless 48 MHz → 24 MHz transition during USB suspend mode without host renegotiation.	Use Scenario: Generating 10 MHz system clock and 1 MHz watchdog timer clock in programmable logic controller with extended temperature range. IC Role / Device Role / Timing Role: Industrial-grade clock source operating from –40 °C to +85 °C with stable 25 MHz crystal reference. Use Value: Maintains <±50 ppm total stability over temperature and voltage - exceeds IEC 61131-2 requirements for PLC timing.

HDMI Audio/Video Timing

Network PHY Clocking

Use Scenario: Generating synchronized pixel clock (74.25 MHz), audio reference (24.576 MHz), and CEC clock (32 kHz) from a single 27 MHz crystal in a set-top box.

IC Role / Device Role / Timing Role: Primary clock source replacing three discrete oscillators; provides deterministic phase relationships between video and audio domains.

Use Value: Reduces BOM count and board area by 66% versus discrete XO solution while maintaining <100 ps jitter for HDMI 1.4 compliance.

Use Scenario: Supplying 125 MHz RMII clock and 25 MHz management clock to Ethernet PHY and MAC in residential gateway.

IC Role / Device Role / Timing Role: Single-chip clock generator delivering two unrelated frequencies with independent voltage levels (3.3 V for PHY, 2.5 V for MAC).

Use Value: Eliminates inter-clock skew and simplifies power sequencing vs. dual-XO design; meets IEEE 802.3u jitter requirements.

USB 2.0 Host Controller

Industrial PLC Timing

Use Scenario: Providing 48 MHz USB clock and 24 MHz auxiliary timer clock to microcontroller in peripheral device.

IC Role / Device Role / Timing Role: Free-running clock synthesizer replacing crystal + buffer; supports dynamic frequency change during suspend/resume.

Use Value: Enables glitchless 48 MHz → 24 MHz transition during USB suspend mode without host renegotiation.

Use Scenario: Generating 10 MHz system clock and 1 MHz watchdog timer clock in programmable logic controller with extended temperature range.

IC Role / Device Role / Timing Role: Industrial-grade clock source operating from –40 °C to +85 °C with stable 25 MHz crystal reference.

Use Value: Maintains <±50 ppm total stability over temperature and voltage - exceeds IEC 61131-2 requirements for PLC timing.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5351B-A-GTR	Includes integrated VCXO and VC pin; supports voltage-controlled tuning (±30 to ±240 ppm) and synchronous clock generation from external reference	Required when system needs PLL lock to external clock (e.g., telecom sync) or adjustable frequency pulling	Select Si5351B-A-GTR only if VCXO functionality is needed; SI5351A-A-GTR lacks VC/CLKIN pins and cannot replace VCXOs
CDCE906PWR	6-output, 3.3 V-only, no internal crystal; requires external 10–210 MHz reference clock and separate crystal oscillator circuit	Suitable for designs with existing high-frequency reference but not for crystal-replacement use cases	Choose CDCE906PWR when external reference is available and lower channel count suffices; SI5351A-A-GTR integrates crystal and supports 8 outputs

Compared with Si5351B-A-GTR and CDCE906PWR, the SI5351A-A-GTR uniquely combines 8-output capability, internal crystal oscillator, and zero-ppm synthesis - making it optimal for cost-driven crystal/XO replacement where VCXO or external reference features are unnecessary.

Availability

SI5351A-A-GTR is available at Aetrix Electronics and suitable for HDMI set-top boxes, Ethernet residential gateways, USB peripheral controllers, and industrial PLCs requiring stable component supply with full lifecycle support.

Supply support for SI5351A-A-GTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Labs is a fabless semiconductor company specializing in timing, wireless, and MCU solutions, with deep expertise in precision clock generation and RF integration.

The Si5351 family was designed specifically to replace discrete crystals, XOs, and fanout buffers in cost-sensitive consumer and industrial electronics - prioritizing integration, I²C configurability, and jitter performance over analog tuning flexibility.

FAQ

What is the maximum output frequency supported by the SI5351A-A-GTR?

The SI5351A-A-GTR supports a maximum output frequency of 160 MHz per channel, verified in Table 5 of the preliminary datasheet Rev. 0.95. This applies to any of its eight outputs (CLK0–CLK7) when configured using the MultiSynth fractional divider architecture. Frequencies above 100 MHz are achievable with reduced drive strength and require CL ≤ 5 pF loading per output.

Does the SI5351A-A-GTR support external clock input (CLKIN) or VCXO functionality?

No, the SI5351A-A-GTR does not support external clock input (CLKIN) or VCXO operation. As confirmed in the functional block diagram (Figure 1) and Section 3.1.2/3.1.3 of the datasheet, only the Si5351B and Si5351C variants include CLKIN or VC pins. The SI5351A-A-GTR relies exclusively on its internal 25/27 MHz crystal oscillator (XA/XB) for all synthesis.

How many independent voltage supplies does the SI5351A-A-GTR require for its outputs?

The SI5351A-A-GTR requires five voltage supplies: one core VDD (2.5 V or 3.3 V) and four independent VDDO rails (VDDOA–VDDOD), each powering a pair of outputs (CLK0–CLK1, CLK2–CLK3, CLK4–CLK5, CLK6–CLK7). Each VDDO can be set to 1.8 V, 2.5 V, or 3.3 V independently - confirmed in Table 1 and Section 3.3 of the SI5351A-A-GTR datasheet.

Can the SI5351A-A-GTR generate spread spectrum clocking on all eight outputs?

Spread spectrum is supported only on outputs derived from PLLA, not PLLB - and only when enabled via I²C register configuration or SSEN pin assertion. As stated in Section 3.4 and Figure 6, spread spectrum is unavailable on PLLB-sourced clocks. The SI5351A-A-GTR's dual-PLL architecture means designers must assign outputs requiring SSC to PLLA-based MultiSynths during configuration.

What crystal specifications are required for reliable operation of the SI5351A-A-GTR?

The SI5351A-A-GTR requires a fundamental-mode AT-cut crystal with frequency 25 MHz or 27 MHz, load capacitance 6–12 pF, ESR ≤ 150 Ω, and drive level ≤ 100 µW - per Table 6 and Section 3.1.1. Internal load capacitors (6/8/10 pF) are configurable via register 183; crystals requiring 12 pF load use internal 10 pF plus 2 pF external caps.

SI5351A-A-GTR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

Type:: Clock Generator

PLL:: Yes

Input:: Crystal

Output:: LVCMOS

Number of Circuits:: 1

Ratio - Input:Output:: 1:3

Differential - Input:Output:: No/No

Frequency - Max:: 200MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 3.6V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 10-MSOP

SI5351A-A-GTR FAQ

1.How can I place an order for SI5351A-A-GTR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5351A-A-GTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5351A-A-GTR reliable?

The price and inventory of SI5351A-A-GTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5351A-A-GTR is usually 5 days.

3.What payment methods are accepted for SI5351A-A-GTR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5351A-A-GTR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5351A-A-GTR?

SI5351A-A-GTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5351A-A-GTR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5351A-A-GTR?

For technical support, including SI5351A-A-GTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5351A-A-GTR requirements.

6.How does Aetrix verify that SI5351A-A-GTR is sourced from the original manufacturer or authorized distributors?

All SI5351A-A-GTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5351A-A-GTR meets industry standards.

7.What is the process for return or replacement of SI5351A-A-GTR?

All SI5351A-A-GTR units undergo pre-shipment inspection (PSI). If there is an issue with SI5351A-A-GTR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5351A-A-GTR part is unused and in its original packaging.

Return procedure for SI5351A-A-GTR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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