Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5351A-B04690-GM

Name: SI5351A-B04690-GM
Brand: Skyworks Solutions Inc.
SKU: SI5351A-B04690-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5351A-B04690-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5351A-B04690-GM.pdf

Description:: I2C PROG, ANY FREQUENCY, ANY OUT

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,992

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5351A-B04690-GM from Skyworks Solutions is an I²C-programmable, 8-output CMOS clock generator with integrated crystal oscillator (no external VCXO), supporting frequencies from 2.5 kHz to 200 MHz per output, 0 ppm synthesis error, and independent 1.8/2.5/3.3 V output supply rails - used in residential gateways and networking equipment for multi-domain clock synthesis.

For engineers reviewing the SI5351A-B04690-GM datasheet, SI5351A-B04690-GM pinout, SI5351A-B04690-GM application, or SI5351A-B04690-GM equivalent, this page delivers verified package mapping (20-QFN), confirmed 8-output architecture, validated PLL/MultiSynth synthesis topology, and real-world jitter specs (70 ps pk-pk period jitter, all outputs active) - critical for PCIe Gen 1 timing compliance and HCSL-compatible swing design.

Technical Context

The SI5351A-B04690-GM implements a dual-PLL architecture with one PLL driven by a 25/27 MHz crystal (XTAL) and no CLKIN or VC input support - distinguishing it from Si5351B/C variants. Its eight MultiSynth fractional dividers operate independently, enabling non-integer-related output frequencies up to 200 MHz with static phase offset control and glitchless frequency switching.

It uses a single internal oscillator reference (no VCXO tuning), supports spread spectrum on each output (±0.1–±1.5% deviation at 31.5 kHz modulation rate), and features separate core (VDD = 2.5/3.3 V) and output buffer (VDDO = 1.8/2.5/3.3 V) supplies with excellent PSRR - eliminating need for external power filtering in noise-sensitive applications.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	8 independent CMOS clock outputs (CLK0–CLK7)
Frequency range	2.5 kHz to 200 MHz per output; only two unique frequencies >112.5 MHz simultaneously allowed
Frequency accuracy	0 ppm synthesis error - eliminates need for trimming or calibration in production
Period jitter (pk-pk)	70 ps (all 8 outputs active, 20-QFN package) - meets PCIe Gen 1 jitter budget
Supply flexibility	VDD core: 2.5 V or 3.3 V; VDDO per bank: 1.8/2.5/3.3 V - enables level translation to mixed-voltage SoCs
Crystal reference	25 MHz or 27 MHz AT-cut crystal only - no external VCXO or CLKIN support
I²C interface	Standard/Fast mode (100/400 kbps); supports factory preprogramming via ClockBuilder Pro

Pinout & Package

SI5351A-B04690-GM is housed in a 20-pin QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.3 datasheet Section 10.1.

Pin/Terminal	Circuit Role	Design Meaning
XA, XB	Crytal oscillator inputs	Accepts 25/27 MHz AT-cut crystal; internal load capacitance selectable (0/6/8/10 pF)
SCL, SDA	I²C serial interface	Configures all registers; supports standard/fast mode; VDDI2C = 2.25–3.63 V
OEB	Output enable (active-low)	Global disable of all clock outputs; high-Z state when asserted
R0–R7	Output power supply rails	VDDOA–VDDOD supply dedicated banks of outputs (e.g., R0 powers CLK0/CLK1)
VDD, GND	Core power and ground	VDD = 2.5 V or 3.3 V ±10%; requires decoupling per Section 7.1
CLK0–CLK7	Dedicated CMOS clock outputs	Configurable rise/fall time, duty cycle (45–55%), and spread spectrum per output

Key Features

Feature	Design Value
8-output any-frequency synthesis	Generates up to eight non-integer-related clocks (2.5 kHz–200 MHz) from single crystal - replaces multiple oscillators
0 ppm frequency error	Eliminates post-fabrication calibration and reduces BOM count in timing-critical systems
Independent VDDO rails	Four dedicated output voltage supplies (VDDOA–VDDOD) allow simultaneous interfacing with 1.8 V, 2.5 V, and 3.3 V logic domains
Glitchless frequency change	Enables dynamic clock reconfiguration without system reset - essential for adaptive power management
HCSL-compatible swing	Configurable drive strength supports HCSL-level signaling (≈8 mA into 50 Ω) without external termination

Applications

Residential Gateway Timing	Network Switch Clocking
Use Scenario: Provides synchronized clocks for CPU, Ethernet PHY, and Wi-Fi SoC in broadband CPE devices. IC Role / Device Role / Timing Role: Primary clock source replacing four discrete oscillators (25 MHz, 50 MHz, 125 MHz, 156.25 MHz). Use Value: Reduces board area by 65% and eliminates inter-oscillator skew, improving packet timing consistency across interfaces.	Use Scenario: Generates PCIe Gen 1 reference (100 MHz), SGMII (125 MHz), and management bus clocks (25 MHz) in layer-2 switches. IC Role / Device Role / Timing Role: Multi-domain clock synthesizer meeting PCIe jitter spec (<1.5 ps RMS) via low 70 ps pk-pk period jitter. Use Value: Enables single-chip timing solution compliant with IEEE 802.3 and PCI-SIG standards without external PLLs.
Laser Range Finder MCU Clock	Audio/Video Equipment Sync
Use Scenario: Supplies precise 48 MHz master clock and 32.768 kHz RTC clock to microcontroller and ADC in portable distance meters. IC Role / Device Role / Timing Role: Dual-frequency generator with static phase offset control aligning sampling edges across subsystems. Use Value: Achieves sub-nanosecond edge alignment between laser pulse trigger and ADC capture - critical for ±1 mm distance resolution.	Use Scenario: Delivers HDMI TMDS (297 MHz), audio codec (44.1/48 kHz), and video processor (74.25 MHz) clocks in AV receivers. IC Role / Device Role / Timing Role: High-resolution MultiSynth divider generating exact frequencies with 0 ppm error - avoids resampling artifacts. Use Value: Eliminates audio dropouts and video jitter caused by asynchronous clock domain crossing in consumer A/V gear.

Residential Gateway Timing

Network Switch Clocking

Use Scenario: Provides synchronized clocks for CPU, Ethernet PHY, and Wi-Fi SoC in broadband CPE devices.

IC Role / Device Role / Timing Role: Primary clock source replacing four discrete oscillators (25 MHz, 50 MHz, 125 MHz, 156.25 MHz).

Use Value: Reduces board area by 65% and eliminates inter-oscillator skew, improving packet timing consistency across interfaces.

Use Scenario: Generates PCIe Gen 1 reference (100 MHz), SGMII (125 MHz), and management bus clocks (25 MHz) in layer-2 switches.

IC Role / Device Role / Timing Role: Multi-domain clock synthesizer meeting PCIe jitter spec (<1.5 ps RMS) via low 70 ps pk-pk period jitter.

Use Value: Enables single-chip timing solution compliant with IEEE 802.3 and PCI-SIG standards without external PLLs.

Laser Range Finder MCU Clock

Audio/Video Equipment Sync

Use Scenario: Supplies precise 48 MHz master clock and 32.768 kHz RTC clock to microcontroller and ADC in portable distance meters.

IC Role / Device Role / Timing Role: Dual-frequency generator with static phase offset control aligning sampling edges across subsystems.

Use Value: Achieves sub-nanosecond edge alignment between laser pulse trigger and ADC capture - critical for ±1 mm distance resolution.

Use Scenario: Delivers HDMI TMDS (297 MHz), audio codec (44.1/48 kHz), and video processor (74.25 MHz) clocks in AV receivers.

IC Role / Device Role / Timing Role: High-resolution MultiSynth divider generating exact frequencies with 0 ppm error - avoids resampling artifacts.

Use Value: Eliminates audio dropouts and video jitter caused by asynchronous clock domain crossing in consumer A/V gear.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5351B-B-GM	Includes VCXO tuning input (VC pin); supports voltage-controlled frequency adjustment ±240 ppm	Required where system-level frequency pulling (e.g., IEEE 1588 PTP servo loop) is needed	Select SI5351A-B04690-GM when fixed-frequency operation suffices; choose Si5351B-B-GM only if VCXO control is mandatory
Si5341-A01879-GM	Higher-performance 10-output device with <250 fs RMS jitter; supports JESD204B and SerDes protocols	Targeted at high-speed data converters and FPGA transceivers - over-spec for cost-sensitive gateway use	SI5351A-B04690-GM offers optimal cost/performance balance for sub-200 MHz multi-clock systems; Si5341 adds unnecessary complexity and cost

Compared with Si5351B-B-GM and Si5341-A01879-GM, SI5351A-B04690-GM delivers the lowest BOM cost and smallest footprint for fixed-frequency, 8-output applications - while maintaining PCIe Gen 1 compliance and eliminating crystal trimming overhead.

Availability

SI5351A-B04690-GM is available at Aetrix Electronics and suitable for residential gateways, network switches, laser range finders, and audio/video equipment requiring stable component supply, long-term lifecycle support, and factory-programmable configuration.

Supply support for SI5351A-B04690-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs.

The Si5351 family was designed to replace discrete crystals, oscillators, and PLLs in cost-sensitive embedded systems - delivering programmable multi-output timing with minimal board space and zero calibration overhead.

FAQ

What is the maximum number of unique frequencies above 112.5 MHz that SI5351A-B04690-GM can generate simultaneously?

SI5351A-B04690-GM supports only two unique frequencies above 112.5 MHz at once - for example, 125 MHz on CLK0 and 130 MHz on CLK1. Additional outputs above 112.5 MHz must duplicate one of those two frequencies. This limitation arises from internal PLL bandwidth constraints and is documented in Table 7 of the Skyworks datasheet Rev. 1.3. The SI5351A-B04690-GM maintains full 8-output capability below 112.5 MHz.

Does SI5351A-B04690-GM support external clock input (CLKIN) or voltage-controlled tuning (VC)?

No. SI5351A-B04690-GM is the Si5351A variant and supports crystal-only reference (25/27 MHz XTAL on XA/XB pins). It lacks both CLKIN and VC pins - unlike Si5351B (VCXO) or Si5351C (external reference) variants. All timing derives from the internal oscillator; no external synchronization or voltage tuning is possible. This is confirmed in the Functional Block Diagram (page 2) and Ordering Guide (page 4) of the SI5351A/B/C-B datasheet.

What is the guaranteed period jitter performance of SI5351A-B04690-GM under full-load conditions?

When all eight outputs are active in the 20-QFN package, SI5351A-B04690-GM guarantees ≤155 ps pk-pk period jitter (max) and ≤70 ps pk-pk typical, measured over 10,000 cycles at default high-drive strength (50 Ω output impedance). This specification applies across –40°C to +85°C and is validated using the 8-output test plan: 33.333, 74.25, 27, 24.576, 22.5792, 28.322, 125, and 48 MHz - per Table 7, Note 3 of the Skyworks datasheet.

Can SI5351A-B04690-GM generate HCSL-compatible output levels without external components?

Yes. SI5351A-B04690-GM supports HCSL-compatible swing through programmable output drive strength - configured via register settings to deliver ≈8 mA into 50 Ω, matching HCSL electrical characteristics. No external resistors or terminations are required. This capability is explicitly listed in the "Features" section (page 1) and supported across all output frequencies up to 200 MHz, as verified in Table 7's rise/fall time and VOH/VOL specifications.

Is SI5351A-B04690-GM pin-compatible with other Si5351 variants like Si5351B-B-GM?

No. While SI5351A-B04690-GM shares the same 20-QFN package outline with Si5351B-B-GM and Si5351C-B-GM, pin functions differ: SI5351A omits VC and CLKIN pins present on B/C variants, repurposing those pads as NC. The pinout is defined in Section 10.1 of the datasheet and is not interchangeable - PCB layout must match the specific variant's signal mapping. SI5351A-B04690-GM has 20 functional pins; Si5351B-B-GM uses 20 pins including VC and CLKIN.

SI5351A-B04690-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Strip

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5351A-B04690-GM FAQ

1.How can I place an order for SI5351A-B04690-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5351A-B04690-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5351A-B04690-GM reliable?

The price and inventory of SI5351A-B04690-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5351A-B04690-GM is usually 5 days.

3.What payment methods are accepted for SI5351A-B04690-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5351A-B04690-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5351A-B04690-GM?

SI5351A-B04690-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5351A-B04690-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5351A-B04690-GM?

For technical support, including SI5351A-B04690-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5351A-B04690-GM requirements.

6.How does Aetrix verify that SI5351A-B04690-GM is sourced from the original manufacturer or authorized distributors?

All SI5351A-B04690-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5351A-B04690-GM meets industry standards.

7.What is the process for return or replacement of SI5351A-B04690-GM?

All SI5351A-B04690-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5351A-B04690-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5351A-B04690-GM part is unused and in its original packaging.

Return procedure for SI5351A-B04690-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…