Skyworks Solutions Inc. SI5351A-B05268-GTR

Overview

SI5351A-B05268-GTR from Skyworks Solutions is an I²C-programmable, 8-output CMOS clock generator with integrated VCXO, designed to replace crystals, crystal oscillators, and discrete PLLs in cost-sensitive embedded systems. It delivers up to eight independent, non-integer-related frequencies from 2.5 kHz to 200 MHz with 0 ppm synthesis error, operates from a 25/27 MHz crystal, and supports 1.8/2.5/3.3 V output voltage levels for mixed-signal timing in audio/video equipment and networking gear.

For engineers reviewing the SI5351A-B05268-GTR datasheet, SI5351A-B05268-GTR pinout, SI5351A-B05268-GTR application, or SI5351A-B05268-GTR equivalent, this device offers precise multi-frequency synthesis, programmable rise/fall times, static phase offset control, glitchless frequency changes, and low period jitter (<70 ps pk-pk) - critical for PCIe Gen 1, HCSL-compatible interfaces, and synchronized multi-domain clocking.

Technical Context

The SI5351A-B05268-GTR implements a dual-PLL architecture (PLLA + PLLB) with high-resolution MultiSynth fractional dividers per output, enabling independent frequency synthesis on all eight outputs. Its input stage accepts only a fixed 25/27 MHz crystal (no CLKIN or VC pins), and it lacks VCXO tuning capability - distinguishing it from Si5351B/C variants.

Each output features configurable drive strength, spread spectrum (±0.1% to ±1.5%), and adjustable delay; core logic runs at 2.5/3.3 V while output buffers support independent 1.8/2.5/3.3 V supply rails. Power-up time is ≤10 ms, and output enable time is ≤10 µs, supporting fast system initialization and dynamic clock gating.

Key Specifications

Pinout & Package

SI5351A-B05268-GTR is housed in a 20-pin QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5351A 20-pin QFN specification (Rev. 1.3, Section 10.1).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5351B-B-GM and Si5351C-B-GM, SI5351A-B05268-GTR provides identical 8-output synthesis capability and jitter performance but omits VC and CLKIN inputs - simplifying design, reducing component count, and lowering cost for free-running clock generation where external synchronization is unnecessary.

Availability

SI5351A-B05268-GTR is available at Aetrix Electronics and suitable for audio/video equipment, networking/communication gear, and handheld instrumentation requiring stable component supply, long-term lifecycle support, and factory-programmed timing configurations.

Supply support for SI5351A-B05268-GTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with emphasis on performance, integration, and reliability.

The Si5351A-B05268-GTR belongs to Skyworks' Si5351 family of I²C-programmable clock generators, engineered to replace discrete timing components in cost-sensitive, space-constrained applications such as consumer AV, networking, and portable instrumentation.

FAQ

What is the maximum number of unique frequencies above 112.5 MHz that SI5351A-B05268-GTR can generate simultaneously?

SI5351A-B05268-GTR supports a maximum of two unique frequencies above 112.5 MHz at the same time (e.g., 125 MHz on CLK0 and 130 MHz on CLK1). Additional outputs above 112.5 MHz must duplicate one of those two frequencies - for example, CLK2–CLK7 may replicate CLK0 or CLK1. This limitation arises from internal PLL bandwidth and divider resource constraints documented in Skyworks Rev. 1.3 datasheet Table 7.

Does SI5351A-B05268-GTR support external clock input (CLKIN) or voltage-controlled tuning (VC)?

No. SI5351A-B05268-GTR is the Si5351A variant and accepts only a 25 MHz or 27 MHz crystal via XA/XB pins. It does not include CLKIN or VC pins - unlike Si5351B (VCXO) or Si5351C (CLKIN + crystal) variants. This is confirmed by its part number suffix "A", functional block diagram (page 2), and absence of VC/CLKIN pins in the 20-QFN pinout (Section 10.1).

What output voltage levels does SI5351A-B05268-GTR support, and how are they configured?

SI5351A-B05268-GTR supports three output voltage levels: 1.8 V, 2.5 V, and 3.3 V, assigned per output bank (VDDOA–VDDOD). Each bank powers two outputs (e.g., VDDOA supplies CLK0/CLK1). Voltage selection is hardware-defined by the voltage applied to each VDDO pin - no register configuration is required. This enables level translation across mixed-voltage SoCs without external level shifters.

Can SI5351A-B05268-GTR generate spread spectrum clocking on individual outputs?

Yes. SI5351A-B05268-GTR supports per-output spread spectrum clocking (SSC) with selectable down-spread (–0.1% to –2.5%) or center-spread (±0.1% to ±1.5%) modulation at 31.5 kHz. SSC is enabled independently for each output via dedicated register bits (Registers 47–49), allowing EMI reduction on noise-sensitive outputs (e.g., video clocks) while maintaining tight jitter on critical timing paths (e.g., PCIe reference).

What is the power-up time and output enable behavior of SI5351A-B05268-GTR?

SI5351A-B05268-GTR achieves valid output clocks within 10 ms after VDD reaches minimum (2.25 V or 3.0 V), per Table 5. Output enable time (OEB pin assertion to stable clock) is ≤10 µs. Both specifications assume CL = 5 pF and fCLKn > 1 MHz. The device also supports PLL bypass mode with sub-1 ms power-up (0.5–1 ms), useful for rapid boot scenarios where initial clock stability is less critical than speed.