Skyworks Solutions Inc. SI5351A-B06002-GT
- Part No.:
- SI5351A-B06002-GT
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- -
- Datasheet:
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SI5351A-B06002-GT.pdf
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Product details
Overview
SI5351A-B06002-GT from Skyworks Solutions is an I²C-programmable 8-output CMOS clock generator with integrated VCXO, designed to replace crystals, crystal oscillators, and discrete PLLs in cost-sensitive embedded systems. It delivers up to eight independent, non-integer-related frequencies from 2.5 kHz to 200 MHz with 0 ppm synthesis error, operates from a 25/27 MHz crystal, and supports 1.8/2.5/3.3 V output voltage levels per bank for mixed-signal timing in networking and audio/video equipment.
For engineers reviewing the SI5351A-B06002-GT datasheet, SI5351A-B06002-GT pinout, SI5351A-B06002-GT application, or SI5351A-B06002-GT equivalent, this device offers programmable spread spectrum, glitchless frequency switching, static phase offset control, and configurable rise/fall times - all critical for PCIe Gen 1–compliant clocking, HCSL-compatible outputs, and low-jitter multi-domain synchronization.
Technical Context
The SI5351A-B06002-GT implements a dual-PLL architecture (PLLA + VCXO-based PLLB) feeding eight independent MultiSynth fractional dividers, enabling simultaneous generation of asynchronous and synchronous clocks. Its input stage accepts only a 25/27 MHz crystal (no CLKIN or VC support), distinguishing it from Si5351B/C variants.
Each output features separate VDDO supply pins (1.8/2.5/3.3 V), programmable drive strength, and adjustable delay. The device uses internal load capacitance (0/6/8/10 pF) for crystal interface and supports spread spectrum modulation at 31.5 kHz with ±0.1–±1.5% deviation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Outputs | 8 independent CMOS clock outputs with individual frequency, phase, and drive control |
| Frequency Range | 2.5 kHz to 200 MHz per output; only two unique frequencies >112.5 MHz simultaneously allowed |
| Output Jitter | <70 ps pk-pk period jitter (typical, all outputs active, 20-QFN package) |
| Supply Voltages | Core VDD: 2.25–3.6 V; Output banks VDDO: 1.71–3.6 V, independently configurable |
| Crystal Reference | 25 or 27 MHz AT-cut crystal only; no external CLKIN or VC input supported |
| I²C Interface | Standard/Fast mode (100/400 kbps); supports register-level configuration and real-time reprogramming |
| Package | 20-pin QFN (4×4 mm, 0.5 mm pitch), RoHS-compliant, thermal resistance θJA = 41°C/W (4-layer board) |
Pinout & Package
The SI5351A-B06002-GT is housed in a 20-pin QFN (4×4 mm, 0.5 mm pitch) package with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.3 datasheet Section 10.1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD | Core supply | 2.25–3.6 V power for logic and PLLs; must be powered before or concurrently with VDDOx |
| VDDOA–VDDOD | Output bank supplies | Four independent 1.71–3.6 V supplies for CLK0–CLK7 groups; enable level translation and noise isolation |
| CLK0–CLK7 | CMOS clock outputs | Eight configurable outputs; each supports programmable frequency, phase offset, spread spectrum, and rise/fall time |
| XA/XB | Crystal oscillator inputs | Differential crystal connection for 25/27 MHz reference; internal load caps (0/6/8/10 pF) eliminate external components |
| SCL/SDA | I²C interface | Two-wire serial bus for configuration; supports standard/fast mode; VDDI2C = 2.25–3.63 V |
| OEB | Output enable | Active-low global output disable; enables fast power-down of all clocks without reconfiguration |
| A0 | I²C address select | Configures LSB of 7-bit I²C address (0x60 or 0x61); allows two devices on same bus |
Key Features
| Feature | Design Value |
|---|---|
| 0 ppm frequency synthesis error | Exact integer/fractional MultiSynth division eliminates cumulative timing drift across multiple clock domains |
| Glitchless frequency switching | Atomic register updates prevent clock interruptions during dynamic reconfiguration - essential for live system tuning |
| Per-output spread spectrum | Independent SSC enable/disable and deviation control per CLKx reduces EMI peaks without affecting other outputs |
| Static phase offset control | 333 ps/step resolution enables precise inter-output skew alignment for DDR or SerDes sampling windows |
| Programmable rise/fall time | Adjustable edge rates minimize signal integrity issues on long traces or high-capacitance loads |
Applications
| Audio/Video Timing | Networking Equipment |
|---|---|
Use Scenario: Generating synchronized sample clocks (e.g., 24.576 MHz, 48 MHz, 74.25 MHz) for ADC/DAC, HDMI, and SPDIF interfaces in AV receivers and soundbars. IC Role / Device Role / Timing Role: Single-chip multi-frequency clock source replacing multiple discrete oscillators and fanout buffers. Use Value: Eliminates board space and BOM cost of 3–4 crystals while maintaining <70 ps jitter required for 24-bit/192 kHz audio fidelity. | Use Scenario: Providing PCIe Gen 1 reference (100 MHz), Ethernet PHY clocks (25/125 MHz), and management controller timing (33.333 MHz) in residential gateways and switches. IC Role / Device Role / Timing Role: Centralized clock generator meeting PCIe Gen 1 jitter compliance (<1.5 ps RMS) and IEEE 802.3 timing margins. Use Value: Enables single-crystal design with deterministic phase relationships between domains, reducing EMI and layout complexity. |
| Industrial Instrumentation | Laser Rangefinding Systems |
Use Scenario: Delivering precise trigger and sampling clocks (e.g., 28.322 MHz, 125 MHz) for high-speed data acquisition modules in handheld oscilloscopes and spectrum analyzers. IC Role / Device Role / Timing Role: Low-jitter, reprogrammable clock engine supporting variable sampling rates and multi-channel synchronization. Use Value: Allows field-upgradable timing configurations via I²C without hardware changes, extending product lifecycle. | Use Scenario: Generating time-of-flight measurement clocks (e.g., 22.5792 MHz, 27 MHz) and laser pulse modulation signals in compact laser distance meters. IC Role / Device Role / Timing Role: Ultra-low-power, small-footprint clock source with sub-ns jitter for picosecond-level time interval accuracy. Use Value: Meets <100 ps pk-pk jitter requirement for ±1 mm distance resolution at 10 m range using TDC-based architectures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5351B-B-GM | Includes VC pin for voltage-controlled tuning (±30–±240 ppm pull range); same 8-output 20-QFN package | Required where dynamic frequency adjustment (e.g., clock recovery, jitter cleanup) is needed | Select SI5351A-B06002-GT when fixed-frequency, crystal-only operation suffices and VCXO complexity is unnecessary |
| Si5351C-B-GM | Supports external CLKIN (10–100 MHz) for synchronous clock generation; lacks VC pin | Necessary when synchronizing to an existing system reference (e.g., GPSDO, master clock) instead of crystal | Choose SI5351A-B06002-GT for standalone, crystal-referenced designs with no external clock source or tuning requirement |
Compared with Si5351B-B-GM and Si5351C-B-GM, the SI5351A-B06002-GT provides identical 8-output capability and jitter performance but omits VC and CLKIN inputs - simplifying design, reducing component count, and lowering cost in free-running clock replacement applications.
Availability
SI5351A-B06002-GT is available at Aetrix Electronics and suitable for networking equipment, audio/video timing systems, and industrial instrumentation requiring stable component supply, long-term manufacturability, and consistent electrical performance across temperature and voltage ranges.
Supply support for SI5351A-B06002-GT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clocking expertise.
The Si5351 family was engineered to replace discrete timing components in cost-sensitive, space-constrained applications - delivering programmable flexibility without sacrificing jitter performance or power efficiency.
FAQ
What is the maximum number of unique frequencies above 112.5 MHz that SI5351A-B06002-GT can generate simultaneously?
The SI5351A-B06002-GT supports only two unique frequencies above 112.5 MHz at any time (e.g., 125 MHz and 130 MHz). Multiple outputs may replicate the same high-frequency signal, but no more than two distinct values >112.5 MHz are permitted - a hardware limitation of the MultiSynth architecture documented in Skyworks Rev. 1.3 datasheet Table 7 note 1.
Does SI5351A-B06002-GT support external clock input (CLKIN) or voltage-controlled tuning (VC)?
No. SI5351A-B06002-GT is the Si5351A variant and accepts only a 25/27 MHz crystal via XA/XB pins. It does not implement CLKIN or VC functionality - those features are exclusive to Si5351B (VC) and Si5351C (CLKIN) variants. This is confirmed by the ordering guide (Table 1) and functional block diagrams in the SI5351A/B/C-B datasheet.
What are the valid output voltage levels supported by SI5351A-B06002-GT?
SI5351A-B06002-GT supports three output voltage levels per bank: 1.8 V (1.71–1.89 V), 2.5 V (2.25–2.75 V), and 3.3 V (3.0–3.6 V). Each VDDOA–VDDOD pin powers a pair of outputs (CLK0/1, CLK2/3, CLK4/5, CLK6/7), enabling mixed-voltage timing for interfacing with diverse logic families without level shifters.
How does SI5351A-B06002-GT achieve 0 ppm frequency synthesis error?
SI5351A-B06002-GT achieves 0 ppm error through exact fractional division using its MultiSynth architecture: output frequency = fVCO / (a + b/c), where a, b, c are programmable integers. With sufficient resolution (up to 28-bit denominator), any rational frequency ratio can be represented precisely - eliminating rounding errors inherent in integer-only dividers or crystal-based oscillators.
Is SI5351A-B06002-GT compatible with PCIe Gen 1 clock requirements?
Yes. SI5351A-B06002-GT meets PCIe Gen 1 jitter specifications: typical period jitter is <70 ps pk-pk (Table 7), well within the PCIe Gen 1 limit of 1.5 ps RMS (~4.2 ps pk-pk assuming Gaussian distribution). Its 100 MHz output capability, programmable spread spectrum, and low-phase-noise PLL architecture make it suitable for PCIe reference clock generation per Skyworks documentation.
SI5351A-B06002-GT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- *
- Package/Case:
- -
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- -
- PLL:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Divider/Multiplier:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- -
- Grade:
- -
- Qualification:
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- Supplier Device Package:
- -
SI5351A-B06002-GT FAQ
1.How can I place an order for SI5351A-B06002-GT through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5351A-B06002-GT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5351A-B06002-GT reliable?
The price and inventory of SI5351A-B06002-GT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5351A-B06002-GT is usually 5 days.
3.What payment methods are accepted for SI5351A-B06002-GT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5351A-B06002-GT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5351A-B06002-GT?
SI5351A-B06002-GT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5351A-B06002-GT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5351A-B06002-GT?
For technical support, including SI5351A-B06002-GT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5351A-B06002-GT requirements.
6.How does Aetrix verify that SI5351A-B06002-GT is sourced from the original manufacturer or authorized distributors?
All SI5351A-B06002-GT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5351A-B06002-GT meets industry standards.
7.What is the process for return or replacement of SI5351A-B06002-GT?
All SI5351A-B06002-GT units undergo pre-shipment inspection (PSI). If there is an issue with SI5351A-B06002-GT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5351A-B06002-GT part is unused and in its original packaging.
Return procedure for SI5351A-B06002-GT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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