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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5351A-B06013-GT

Name: SI5351A-B06013-GT
Brand: Skyworks Solutions Inc.
SKU: SI5351A-B06013-GT
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5351A-B06013-GT

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5351A-B06013-GT.pdf

Description:: I2C PROG, ANY FREQUENCY, ANY OUT

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Product details

Overview

SI5351A-B06013-GT from Skyworks Solutions is an I²C-programmable, 8-output CMOS clock generator with integrated VCXO architecture, generating frequencies from 2.5 kHz to 200 MHz per output with 0 ppm synthesis error. It operates from a 25 or 27 MHz crystal reference and supports independent 1.8/2.5/3.3 V output supply rails (VDDO), enabling level translation for mixed-voltage systems such as FPGA clocking and audio/video timing.

For engineers reviewing the SI5351A-B06013-GT datasheet, SI5351A-B06013-GT pinout, SI5351A-B06013-GT application, or SI5351A-B06013-GT equivalent, this device serves as a programmable replacement for crystals, crystal oscillators, and VCXOs in cost-sensitive embedded timing applications requiring multi-frequency, low-jitter clock distribution without custom pullable crystals.

Technical Context

The SI5351A-B06013-GT implements a dual-PLL architecture with one PLL dedicated to VCXO operation and the other supporting spread-spectrum or free-running modes. Its MultiSynth fractional dividers provide independent frequency synthesis per output, enabling non-integer-related clocks across all eight outputs.

It features configurable rise/fall time control, static phase offset adjustment, glitchless frequency transitions, and separate core (VDD) and output (VDDO) supply domains-supporting simultaneous 1.8 V, 2.5 V, and 3.3 V output swings on different pins without external level shifters.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	8 independent CMOS clock outputs (CLK0–CLK7)
Frequency range	2.5 kHz to 200 MHz per output; two unique frequencies >112.5 MHz simultaneously allowed
Period jitter (pk-pk)	< 70 ps typical (all outputs active, 20-QFN package)
VCXO tuning range	±240 ppm max at 3.3 V VDD; linear gain of 18–150 ppm/V
Supply voltages	VDD = 2.25–3.6 V (core); VDDOx = 1.71–3.6 V per output bank (independent rail support)
I²C interface	Standard/Fast Mode (100/400 kbps); supports VDDI2C = 2.25–3.63 V
Crystal reference	25 or 27 MHz AT-cut crystal only; internal load capacitance selectable (0/6/8/10 pF)

Pinout & Package

SI5351A-B06013-GT is housed in a 20-pin QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5351A 20-pin QFN specification (Rev. 1.3, Section 10.1).

Pin/Terminal	Circuit Role	Design Meaning
XA, XB	Crystal oscillator input	Connects to 25/27 MHz AT-cut crystal; internal load caps configurable (0–10 pF)
CLK0–CLK7	CMOS clock outputs	Eight independent outputs; each assigned to VDDOA–VDDOD supply banks for voltage-level flexibility
VDDOA–VDDOD	Output buffer supply rails	Four independent 1.8/2.5/3.3 V supplies for output banks A–D (each powers two CLK outputs)
VDD	Core logic supply	2.25–3.6 V core power; must be powered before or concurrently with all VDDOx rails
SCL, SDA	I²C configuration interface	Supports 100/400 kbps; VDDI2C = 2.25–3.63 V; requires external pull-ups
OEB	Output enable (active-low)	Global enable/disable of all clock outputs; asynchronous, no glitch during transition
VC	VCXO control voltage input	Accepts 0–VDD tuning voltage; enables ±240 ppm pull range with high linearity (±5% error)

Key Features

Feature	Design Value
0 ppm frequency synthesis error	Exact integer and fractional frequency generation per output using MultiSynth dividers-eliminates need for multiple fixed-frequency crystals
Independent output voltage rails	VDDOA–VDDOD allow simultaneous 1.8 V, 2.5 V, and 3.3 V CMOS outputs-enables direct interfacing with mixed-voltage FPGAs and SoCs
Glitchless frequency reprogramming	I²C writes update output frequencies without clock interruption-critical for live system reconfiguration and dynamic power management
Configurable spread spectrum	Per-output down-spread (–0.1% to –2.5%) or center-spread (±0.1% to ±1.5%) at 31.5 kHz modulation rate-reduces EMI in noise-sensitive applications
Static phase offset control	Programmable 333 ps/step phase alignment between any two outputs-supports precise timing skew compensation in parallel data paths

Applications

Audio/Video Timing	Networking Equipment
Use Scenario: Generating synchronized pixel clocks (74.25 MHz), audio master clocks (24.576 MHz), and HDMI TMDS clocks (148.5 MHz) in AV receivers and set-top boxes. IC Role / Device Role / Timing Role: Single-chip multi-domain clock source replacing discrete crystal oscillators and fanout buffers. Use Value: Eliminates board space and BOM cost of four separate oscillators while maintaining <70 ps period jitter across all domains.	Use Scenario: Providing PCIe Gen1 reference clocks (100 MHz), Ethernet PHY clocks (25/125 MHz), and CPU/system clocks (33.333/125 MHz) in residential gateways and switches. IC Role / Device Role / Timing Role: Programmable clock generator with VCXO support for frequency margining and jitter tolerance testing. Use Value: Enables factory calibration via VC pin tuning and eliminates need for expensive pullable crystals in volume production.
FPGA Development Platforms	Laser Range Finders
Use Scenario: Supplying configurable clocks to Xilinx Artix-7 and Intel Cyclone V FPGA banks requiring 1.8 V, 2.5 V, and 3.3 V logic levels. IC Role / Device Role / Timing Role: Voltage-flexible clock distributor with independent per-bank VDDO rails and glitchless reprogramming. Use Value: Allows runtime clock frequency changes during FPGA bitstream loading or partial reconfiguration without reset.	Use Scenario: Driving time-of-flight (ToF) sensor timing circuits requiring ultra-low-jitter 27 MHz and 48 MHz clocks for pulse generation and echo sampling. IC Role / Device Role / Timing Role: Low-phase-noise clock source with <70 ps pk-pk period jitter and adjustable rise/fall times for optimal signal integrity. Use Value: Reduces timing uncertainty in sub-nanosecond ToF measurements by minimizing clock edge uncertainty.

Audio/Video Timing

Networking Equipment

Use Scenario: Generating synchronized pixel clocks (74.25 MHz), audio master clocks (24.576 MHz), and HDMI TMDS clocks (148.5 MHz) in AV receivers and set-top boxes.

IC Role / Device Role / Timing Role: Single-chip multi-domain clock source replacing discrete crystal oscillators and fanout buffers.

Use Value: Eliminates board space and BOM cost of four separate oscillators while maintaining <70 ps period jitter across all domains.

Use Scenario: Providing PCIe Gen1 reference clocks (100 MHz), Ethernet PHY clocks (25/125 MHz), and CPU/system clocks (33.333/125 MHz) in residential gateways and switches.

IC Role / Device Role / Timing Role: Programmable clock generator with VCXO support for frequency margining and jitter tolerance testing.

Use Value: Enables factory calibration via VC pin tuning and eliminates need for expensive pullable crystals in volume production.

FPGA Development Platforms

Laser Range Finders

Use Scenario: Supplying configurable clocks to Xilinx Artix-7 and Intel Cyclone V FPGA banks requiring 1.8 V, 2.5 V, and 3.3 V logic levels.

IC Role / Device Role / Timing Role: Voltage-flexible clock distributor with independent per-bank VDDO rails and glitchless reprogramming.

Use Value: Allows runtime clock frequency changes during FPGA bitstream loading or partial reconfiguration without reset.

Use Scenario: Driving time-of-flight (ToF) sensor timing circuits requiring ultra-low-jitter 27 MHz and 48 MHz clocks for pulse generation and echo sampling.

IC Role / Device Role / Timing Role: Low-phase-noise clock source with <70 ps pk-pk period jitter and adjustable rise/fall times for optimal signal integrity.

Use Value: Reduces timing uncertainty in sub-nanosecond ToF measurements by minimizing clock edge uncertainty.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5351B-B-GM	Same 20-QFN package and 8-output capability, but includes full VCXO functionality with wider tuning range (±240 ppm) and dual-PLL architecture	Required when synchronous clock locking to external voltage control or frequency margining is needed	Select SI5351A-B06013-GT for crystal-only reference designs; choose Si5351B-B-GM if VCXO tuning is mandatory
Si5341-A02849-GM	Higher-performance 10-output clock generator with integrated jitter cleaner (125 fs RMS), supports JESD204B and PCIe Gen4	Targeted at high-speed serial interfaces requiring sub-200 fs jitter; not drop-in compatible due to different pinout and register map	Use SI5351A-B06013-GT for cost-sensitive, general-purpose multi-clock generation; upgrade to Si5341 for JESD204B or ultra-low-jitter applications

Compared with Si5351B-B-GM and Si5341-A02849-GM, SI5351A-B06013-GT delivers optimal balance of 8-output flexibility, crystal-only simplicity, and sub-70 ps jitter at lowest BOM cost-making it ideal for consumer AV, gateway, and industrial embedded timing where VCXO or ultra-low jitter is unnecessary.

Availability

SI5351A-B06013-GT is available at Aetrix Electronics and suitable for audio/video equipment, residential gateways, and FPGA-based embedded systems requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.

Supply support for SI5351A-B06013-GT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs.

The Si5351 family is designed for cost-sensitive, multi-frequency clock generation in consumer, industrial, and communications equipment-replacing discrete crystals, oscillators, and PLLs with a single programmable IC.

FAQ

What is the maximum number of unique frequencies above 112.5 MHz that SI5351A-B06013-GT can generate simultaneously?

The SI5351A-B06013-GT supports up to two unique frequencies above 112.5 MHz at the same time-for example, 125 MHz on CLK0 and 130 MHz on CLK1. Additional outputs may replicate those frequencies (e.g., 125 MHz on CLK0–CLK3), but no third distinct frequency >112.5 MHz is permitted. This limitation arises from internal PLL bandwidth constraints and is specified in Table 7 of the Skyworks datasheet Rev. 1.3.

Does SI5351A-B06013-GT support external clock input (CLKIN) or only crystal reference?

SI5351A-B06013-GT supports crystal reference only (25 or 27 MHz on XA/XB pins) and does not support external CLKIN. The "A" variant is explicitly defined in the Skyworks ordering guide (Table 1) as XTAL-only; CLKIN capability is reserved for Si5351C variants. Attempting to drive CLKIN on SI5351A-B06013-GT will not yield functional clock synthesis.

Can SI5351A-B06013-GT generate HCSL-compatible output swing?

Yes, SI5351A-B06013-GT supports HCSL-compatible swing through programmable output drive strength and termination control. As stated in the Features section of the datasheet, it "Supports HCSL compatible swing" - achieved by configuring output impedance and DC bias via register settings to match HCSL's 17 mA current-source behavior into 50 Ω loads.

What is the guaranteed period jitter performance of SI5351A-B06013-GT under full-load conditions?

Under full-load conditions (all 8 outputs active, 20-QFN package), SI5351A-B06013-GT guarantees period jitter ≤155 ps pk-pk (max) and typically achieves <70 ps pk-pk, as specified in Table 7 of the Skyworks datasheet Rev. 1.3. This measurement assumes default high-drive strength (50 Ω output impedance) and CL = 5 pF load.

Is SI5351A-B06013-GT pin-compatible with other Si5351 variants like Si5351B or Si5351C in the same 20-QFN package?

Yes, SI5351A-B06013-GT shares identical 20-QFN pinout and footprint with Si5351B and Si5351C variants (per Section 10.1–10.3 of the datasheet), including matching assignments for XA/XB, CLK0–CLK7, VDDOA–VDDOD, SCL/SDA, OEB, and VC. However, unused pins (e.g., CLKIN on Si5351A) must remain unconnected-not tied high/low-to avoid unintended behavior.

SI5351A-B06013-GT Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tube

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5351A-B06013-GT FAQ

1.How can I place an order for SI5351A-B06013-GT through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5351A-B06013-GT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5351A-B06013-GT reliable?

The price and inventory of SI5351A-B06013-GT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5351A-B06013-GT is usually 5 days.

3.What payment methods are accepted for SI5351A-B06013-GT?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5351A-B06013-GT transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5351A-B06013-GT?

SI5351A-B06013-GT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5351A-B06013-GT order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5351A-B06013-GT?

For technical support, including SI5351A-B06013-GT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5351A-B06013-GT requirements.

6.How does Aetrix verify that SI5351A-B06013-GT is sourced from the original manufacturer or authorized distributors?

All SI5351A-B06013-GT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5351A-B06013-GT meets industry standards.

7.What is the process for return or replacement of SI5351A-B06013-GT?

All SI5351A-B06013-GT units undergo pre-shipment inspection (PSI). If there is an issue with SI5351A-B06013-GT, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5351A-B06013-GT part is unused and in its original packaging.

Return procedure for SI5351A-B06013-GT:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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