Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5351A-B06302-GM

Name: SI5351A-B06302-GM
Brand: Skyworks Solutions Inc.
SKU: SI5351A-B06302-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5351A-B06302-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5351A-B06302-GM.pdf

Description:: I2C PROG, ANY FREQUENCY, ANY OUT

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:3,407

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5351A-B06302-GM from Skyworks Solutions is an I²C-programmable 8-output CMOS clock generator with integrated VCXO, designed to replace crystals, crystal oscillators, and discrete PLLs in cost-sensitive embedded systems. It delivers up to eight independent, non-integer-related frequencies from 2.5 kHz to 200 MHz with 0 ppm synthesis error, operates from a 25 or 27 MHz fixed-frequency crystal, and supports configurable output voltage levels (1.8/2.5/3.3 V) for mixed-signal timing in audio/video equipment and networking hardware.

For engineers reviewing the SI5351A-B06302-GM datasheet, SI5351A-B06302-GM pinout, SI5351A-B06302-GM application, or SI5351A-B06302-GM equivalent, this device offers verified I²C configurability, sub-100 ps period jitter, spread spectrum control per output, static phase offset adjustment, and glitchless frequency switching - all critical for PCIe Gen 1–compliant clocking and multi-domain synchronization.

Technical Context

The SI5351A-B06302-GM implements a dual-PLL architecture with one PLL dedicated to VCXO operation and the other supporting free-running synthesis; both feed eight independent MultiSynth fractional dividers. Its input stage accepts only a 25/27 MHz crystal (no CLKIN or VC pin support), confirming it as the Si5351A variant without external reference or voltage-controlled tuning capability.

Each output features programmable rise/fall time, adjustable delay, and separate VDDO supply pins enabling level translation across 1.8 V, 2.5 V, or 3.3 V logic domains. The device uses internal load capacitance (0/6/8/10 pF) for crystal interface and supports HCSL-compatible swing via drive strength configuration.

Key Specifications

Parameter	Value and Actual Design Meaning
Outputs	8 independent CMOS clock outputs (CLK0–CLK7)
Frequency Range	2.5 kHz to 200 MHz per output; two unique frequencies >112.5 MHz allowed simultaneously
Period Jitter	< 70 ps pk-pk typical (all outputs active, 20-QFN package)
Core Supply	2.5 V or 3.3 V ±10%; independent VDDO supplies (1.8/2.5/3.3 V) per output group
Crystal Reference	25 MHz or 27 MHz AT-cut crystal only; no CLKIN or VC support
I²C Interface	Standard/Fast mode (100/400 kbps); supports register-level configuration and real-time reprogramming
Package	20-pin QFN (4 mm × 4 mm, 0.5 mm pitch), RoHS-compliant, moisture sensitivity level 3

Pinout & Package

SI5351A-B06302-GM is housed in a 20-pin QFN (4 mm × 4 mm) package with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.3 datasheet Section 10.1.

Pin/Terminal	Circuit Role	Design Meaning
XA, XB	Crystal oscillator inputs	Connect 25/27 MHz AT-cut crystal; internal load capacitance selectable (0/6/8/10 pF)
SCL, SDA	I²C serial interface	Two-wire bus for configuration; supports standard/fast mode; pull-up required externally
OEB	Output enable bar	Active-low global output disable; high-impedance state when asserted
VDD, VDDOx	Power supply rails	VDD = core logic (2.5/3.3 V); VDDOA/B/C/D = independent output buffer supplies (1.8/2.5/3.3 V)
CLK0–CLK7	Differential-capable CMOS outputs	Eight configurable clock outputs; each supports rise/fall time control, spread spectrum, and phase offset
GND, EPAD	Ground and thermal pad	EPAD must be soldered to PCB ground plane for thermal and electrical performance

Key Features

Feature	Design Value
0 ppm frequency synthesis error	Exact frequency generation at each output using fractional MultiSynth dividers, eliminating need for multiple crystals
Glitchless frequency switching	Seamless transition between frequencies without clock interruption - essential for dynamic reconfiguration in FPGA or SoC systems
Configurable spread spectrum per output	Reduces EMI by applying selectable down-spread (–0.1% to –2.5%) or center-spread (±0.1% to ±1.5%) modulation independently on each CLKx
Static phase offset control	Adjustable phase alignment between outputs in 333 ps steps - enables precise timing coordination across multiple ICs
Independent output voltage supplies	VDDOA/B/C/D allow mixing of 1.8 V, 2.5 V, and 3.3 V logic domains on same device - simplifies power domain bridging

Applications

Audio/Video Timing	Networking Equipment
Use Scenario: Generating synchronized pixel clocks (74.25 MHz), audio master clocks (24.576 MHz), and HDMI TMDS clocks (125 MHz) in AV receivers and set-top boxes. IC Role / Device Role / Timing Role: Single-chip multi-domain clock source replacing four discrete oscillators and reducing board space by >60%. Use Value: Eliminates inter-clock skew and jitter accumulation across domains while supporting HCSL-compatible swing for display interfaces.	Use Scenario: Providing PCIe Gen 1 reference clocks (100 MHz), Ethernet PHY clocks (25/125 MHz), and management controller clocks (33.333 MHz) in residential gateways and switches. IC Role / Device Role / Timing Role: PCIe-compliant clock generator meeting <70 ps period jitter requirement across all eight outputs. Use Value: Enables single-device clock tree for mixed-speed interfaces without external fanout buffers or PLLs.
Industrial Instrumentation	Laser Rangefinders
Use Scenario: Delivering precise trigger clocks (10–50 MHz), ADC sampling clocks (27 MHz), and microcontroller system clocks (48 MHz) in handheld test meters and data loggers. IC Role / Device Role / Timing Role: Low-power, crystal-replacement timing engine operating over –40°C to +85°C ambient range. Use Value: Reduces BOM count and improves long-term frequency stability vs. discrete crystal oscillators under thermal cycling.	Use Scenario: Generating laser diode pulse timing (28.322 MHz), time-of-flight measurement clocks (22.5792 MHz), and signal processing clocks (33.333 MHz) in compact rangefinding modules. IC Role / Device Role / Timing Role: Ultra-low-jitter (<95 ps pk-pk) clock source enabling sub-nanosecond time resolution. Use Value: Supports direct digital synthesis of precise pulse intervals without external jitter cleaners or delay lines.

Audio/Video Timing

Networking Equipment

Use Scenario: Generating synchronized pixel clocks (74.25 MHz), audio master clocks (24.576 MHz), and HDMI TMDS clocks (125 MHz) in AV receivers and set-top boxes.

IC Role / Device Role / Timing Role: Single-chip multi-domain clock source replacing four discrete oscillators and reducing board space by >60%.

Use Value: Eliminates inter-clock skew and jitter accumulation across domains while supporting HCSL-compatible swing for display interfaces.

Use Scenario: Providing PCIe Gen 1 reference clocks (100 MHz), Ethernet PHY clocks (25/125 MHz), and management controller clocks (33.333 MHz) in residential gateways and switches.

IC Role / Device Role / Timing Role: PCIe-compliant clock generator meeting <70 ps period jitter requirement across all eight outputs.

Use Value: Enables single-device clock tree for mixed-speed interfaces without external fanout buffers or PLLs.

Industrial Instrumentation

Laser Rangefinders

Use Scenario: Delivering precise trigger clocks (10–50 MHz), ADC sampling clocks (27 MHz), and microcontroller system clocks (48 MHz) in handheld test meters and data loggers.

IC Role / Device Role / Timing Role: Low-power, crystal-replacement timing engine operating over –40°C to +85°C ambient range.

Use Value: Reduces BOM count and improves long-term frequency stability vs. discrete crystal oscillators under thermal cycling.

Use Scenario: Generating laser diode pulse timing (28.322 MHz), time-of-flight measurement clocks (22.5792 MHz), and signal processing clocks (33.333 MHz) in compact rangefinding modules.

IC Role / Device Role / Timing Role: Ultra-low-jitter (<95 ps pk-pk) clock source enabling sub-nanosecond time resolution.

Use Value: Supports direct digital synthesis of precise pulse intervals without external jitter cleaners or delay lines.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5351A-B-GM	No factory programming; blank configuration requiring full I²C initialization at boot	Same 8-output, crystal-only functionality but lacks preloaded firmware for immediate operation	Select SI5351A-B06302-GM when factory-programmed startup sequence and validated frequency plan are required.
Si5351B-B-GM	Includes VC pin and internal VCXO; supports voltage-controlled tuning (±30 to ±240 ppm) and external CLKIN	Enables synchronous clocking and frequency pulling - unsuitable where only free-running crystal-based clocks are needed	Choose Si5351B-B-GM only if VCXO functionality or external reference input is explicitly required in the design.

Compared with Si5351A-B-GM, SI5351A-B06302-GM provides guaranteed factory-programmed configuration and validated timing performance out-of-box, while Si5351B-B-GM adds VCXO flexibility at the cost of increased complexity and higher component cost - making SI5351A-B06302-GM optimal for fixed-frequency, low-risk production deployments.

Availability

SI5351A-B06302-GM is available at Aetrix Electronics and suitable for audio/video equipment, networking infrastructure, and industrial instrumentation requiring stable component supply, consistent factory programming, and guaranteed jitter performance across temperature.

Supply support for SI5351A-B06302-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for wireless, automotive, and industrial markets.

The Si5351 family was engineered to replace discrete timing components with a single, software-configurable clock generator - targeting cost-sensitive, space-constrained applications in consumer electronics, communications, and test equipment.

FAQ

What is the exact crystal frequency supported by SI5351A-B06302-GM?

The SI5351A-B06302-GM supports only 25 MHz or 27 MHz AT-cut fundamental-mode crystals. These frequencies serve as the sole reference for its internal oscillator and PLLs; no external clock input (CLKIN) or voltage-controlled tuning (VC) is available in this Si5351A variant. Crystal load capacitance is internally configurable to 0, 6, 8, or 10 pF.

Does SI5351A-B06302-GM support spread spectrum clocking?

Yes, SI5351A-B06302-GM supports configurable spread spectrum clocking on each output independently. It offers selectable down-spread (–0.1% to –2.5%) or center-spread (±0.1% to ±1.5%) modulation at a fixed 31.5 kHz rate. This feature is enabled per-output via I²C register writes and reduces electromagnetic interference without affecting functional timing margins.

What is the maximum number of unique high-frequency outputs supported by SI5351A-B06302-GM?

SI5351A-B06302-GM allows only two unique output frequencies above 112.5 MHz simultaneously - for example, 125 MHz on CLK0 and 130 MHz on CLK1. Additional outputs above 112.5 MHz must duplicate one of those two frequencies. This limitation arises from internal PLL bandwidth and MultiSynth divider resolution constraints documented in Skyworks Rev. 1.3 datasheet Table 7.

Can SI5351A-B06302-GM generate sub-10 MHz clocks?

Yes, SI5351A-B06302-GM can generate frequencies as low as 2.5 kHz using its integer division stage following the MultiSynth fractional divider. This capability enables direct replacement of low-frequency RTC clocks, microcontroller watchdog timers, and UART baud-rate generators without external dividers or additional timing ICs.

Is SI5351A-B06302-GM pin-compatible with other Si5351 variants?

No, SI5351A-B06302-GM shares the same 20-pin QFN package and pinout as other Si5351A/B/C variants in the 20-QFN option, but functional pin compatibility is limited: the VC and CLKIN pins are no-connects in this Si5351A version and must remain unconnected or tied appropriately. Electrical behavior differs significantly due to absence of VCXO circuitry and external reference path.

SI5351A-B06302-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Strip

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5351A-B06302-GM FAQ

1.How can I place an order for SI5351A-B06302-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5351A-B06302-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5351A-B06302-GM reliable?

The price and inventory of SI5351A-B06302-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5351A-B06302-GM is usually 5 days.

3.What payment methods are accepted for SI5351A-B06302-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5351A-B06302-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5351A-B06302-GM?

SI5351A-B06302-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5351A-B06302-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5351A-B06302-GM?

For technical support, including SI5351A-B06302-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5351A-B06302-GM requirements.

6.How does Aetrix verify that SI5351A-B06302-GM is sourced from the original manufacturer or authorized distributors?

All SI5351A-B06302-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5351A-B06302-GM meets industry standards.

7.What is the process for return or replacement of SI5351A-B06302-GM?

All SI5351A-B06302-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5351A-B06302-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5351A-B06302-GM part is unused and in its original packaging.

Return procedure for SI5351A-B06302-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…