Skyworks Solutions Inc. SI5351A-B06559-GTR

Overview

SI5351A-B06559-GTR from Skyworks Solutions is an I²C-programmable, 8-output CMOS clock generator with integrated VCXO, designed to replace crystals, crystal oscillators, and discrete PLLs in cost-sensitive embedded systems. It delivers up to eight independent, non-integer-related frequencies from 2.5 kHz to 200 MHz per output, with 0 ppm synthesis error, low period jitter (<70 ps pk-pk), and configurable output voltage (1.8/2.5/3.3 V) - enabling use in audio/video timing, networking PHY clocks, and FPGA reference clocking.

For engineers reviewing the SI5351A-B06559-GTR datasheet, SI5351A-B06559-GTR pinout, SI5351A-B06559-GTR application, or SI5351A-B06559-GTR equivalent, this device supports I²C configuration of individual output rise/fall times, spread spectrum (±0.1–±2.5%), static phase offset, and glitchless frequency changes - critical for EMI reduction, multi-domain synchronization, and production-level clock tree validation.

Technical Context

The SI5351A-B06559-GTR implements a dual-PLL architecture: PLL A accepts a 25/27 MHz crystal reference (XTAL), while PLL B operates as a highly linear VCXO with tunable pull range (±30 to ±240 ppm) controlled via the VC pin. Each PLL feeds eight independent MultiSynth fractional dividers, enabling simultaneous generation of asynchronous or synchronized outputs.

It features separate core (VDD = 2.5/3.3 V) and output (VDDOx = 1.8/2.5/3.3 V) supply rails, excellent PSRR (>60 dB), and programmable drive strength. The device supports HCSL-compatible swing and PCIe Gen 1 compliance, with all outputs capable of static phase offset adjustment and independent spread-spectrum modulation.

Key Specifications

Pinout & Package

SI5351A-B06559-GTR is housed in a 20-pin QFN (4×4 mm, 0.5 mm pitch) package with exposed thermal pad. Pin functions are validated per Skyworks Si5351A 20-pin QFN specification (Rev. 1.3, Section 10.1).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5351B-B-GM and CDCE906PWR, SI5351A-B06559-GTR offers the highest output count (8), lowest jitter (<70 ps), and most flexible voltage support (1.8/2.5/3.3 V per group), making it ideal for complex, mixed-voltage embedded systems requiring precise, software-defined clock trees.

Availability

SI5351A-B06559-GTR is available at Aetrix Electronics and suitable for audio/video equipment, networking infrastructure, and FPGA-based industrial controllers requiring stable component supply, long-term lifecycle support, and verified second-source alternatives.

Supply support for SI5351A-B06559-GTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for wireless, automotive, and industrial markets.

The Si5351 family was engineered to replace discrete timing components with a single, field-programmable clock generator - targeting cost-sensitive, space-constrained applications in consumer electronics, networking, and instrumentation where flexibility, low jitter, and rapid design iteration are essential.

FAQ

What is the maximum number of unique frequencies above 112.5 MHz that SI5351A-B06559-GTR can generate simultaneously?

SI5351A-B06559-GTR supports only two unique frequencies above 112.5 MHz at any time (e.g., 125 MHz on CLK0 and 130 MHz on CLK1). Additional outputs above 112.5 MHz must duplicate one of those two frequencies. This constraint arises from internal PLL bandwidth and MultiSynth divider resolution limits, as specified in Skyworks Rev. 1.3, Table 7 note 1. SI5351A-B06559-GTR maintains full 8-output capability below 112.5 MHz.

Does SI5351A-B06559-GTR require an external crystal, and what are the acceptable values?

Yes, SI5351A-B06559-GTR requires a 25 MHz or 27 MHz fundamental-mode AT-cut crystal connected to XA/XB pins. Load capacitance must be 6–12 pF; internal capacitors (0/6/8/10 pF) can be configured via register 183. Crystals with 12 pF requirement need ≤2 pF additional external capacitance. SI5351A-B06559-GTR does not accept CLKIN or VC inputs - it is the Si5351A variant, not B or C.

Can SI5351A-B06559-GTR generate different output voltage levels on its eight clocks?

Yes, SI5351A-B06559-GTR provides four independent VDDO supply rails (VDDOA–VDDOD), each powering two outputs (e.g., VDDOA powers CLK0/CLK1). Each rail accepts 1.8 V, 2.5 V, or 3.3 V, enabling mixed-voltage clocking - such as 1.8 V for FPGA I/O banks and 3.3 V for legacy MCU peripherals - without level shifters. This is confirmed in Skyworks Rev. 1.3, Table 3 and Section 4.3.

What is the typical period jitter performance of SI5351A-B06559-GTR under full-load conditions?

Under full-load conditions (all 8 outputs active, 20-QFN package), SI5351A-B06559-GTR delivers typical period jitter of 70 ps pk-pk, with a maximum of 155 ps pk-pk across –40°C to +85°C. This measurement assumes default high-drive strength (50 Ω output impedance) and 5 pF load, as specified in Skyworks Rev. 1.3, Table 7. Jitter improves significantly with fewer active outputs or lower frequencies.

Is SI5351A-B06559-GTR compatible with PCIe Gen 1 timing requirements?

Yes, SI5351A-B06559-GTR is explicitly stated as PCIe Gen 1 compatible in Skyworks documentation (Rev. 1.3, Features section). Its <70 ps typical period jitter, programmable spread spectrum, and 100 MHz output capability meet PCIe Gen 1 reference clock specifications (PCI-SIG® Base Spec 1.1, §4.3.1), making it suitable for endpoint clocking in embedded PCIe bridges and add-in cards.