Skyworks Solutions Inc. SI5351A-B06884-GTR
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- SI5351A-B06884-GTR
- Manufacturer:
- Skyworks Solutions Inc.
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- -
- Datasheet:
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SI5351A-B06884-GTR.pdf
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Product details
Overview
SI5351A-B06884-GTR from Skyworks Solutions is an I²C-programmable, 8-output CMOS clock generator with integrated VCXO, designed to replace crystals, crystal oscillators, and discrete PLLs in cost-sensitive embedded systems. It delivers up to eight independent, non-integer-related frequencies from 2.5 kHz to 200 MHz with 0 ppm synthesis error, operates from a 25 or 27 MHz crystal, and supports configurable output voltages (1.8/2.5/3.3 V) for mixed-signal timing in networking and audio/video equipment.
For engineers reviewing the SI5351A-B06884-GTR datasheet, SI5351A-B06884-GTR pinout, SI5351A-B06884-GTR application, or SI5351A-B06884-GTR equivalent, key selection criteria include its 20-QFN package with 20 pins, VCXO tuning range (±240 ppm at 3.3 V), <70 ps peak-to-peak period jitter, I²C programmability, and support for spread spectrum and static phase offset - all critical for PCIe Gen 1–compliant clocking and multi-domain synchronization.
Technical Context
The SI5351A-B06884-GTR implements a dual-PLL architecture: PLL A accepts either the internal 25/27 MHz crystal oscillator or external CLKIN (10–100 MHz), while PLL B functions as a highly linear VCXO with voltage-controlled tuning via the VC pin. Each PLL feeds eight independent MultiSynth fractional dividers, enabling exact frequency synthesis per output without integer constraints.
Its output stage features separate VDDO supply pins (1.8/2.5/3.3 V) per bank, programmable rise/fall time control, glitchless frequency transitions, and configurable spread spectrum (±0.1% to ±1.5%, 31.5 kHz modulation). The device supports static phase offset adjustment and HCSL-compatible swing, making it suitable for low-jitter, multi-voltage clock distribution in space-constrained designs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count | 8 independent CMOS clock outputs (CLK0–CLK7) |
| Frequency range | 2.5 kHz to 200 MHz per output; only two unique frequencies >112.5 MHz simultaneously |
| Period jitter | <70 ps pk-pk (all outputs active, 20-QFN package) |
| VCXO pull range | Configurable ±240 ppm at 3.3 V supply |
| Supply flexibility | Core VDD: 2.5 V or 3.3 V; Output VDDO: 1.8 V, 2.5 V, or 3.3 V per bank |
| I²C interface | Standard/Fast mode (100/400 kbps); supports register-based configuration and real-time reprogramming |
| Crystal reference | 25 MHz or 27 MHz AT-cut crystal; internal load capacitance options (0/6/8/10 pF) |
Pinout & Package
SI5351A-B06884-GTR is housed in a 20-pin QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are validated per Skyworks Si5351A 20-pin QFN specification (Rev. 1.3, Section 10.1).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| XA, XB | Crystal oscillator input | Accepts 25 or 27 MHz fundamental-mode AT-cut crystal; internal load caps configurable |
| CLK0–CLK7 | CMOS clock outputs | Eight independent, programmable-frequency outputs; each with dedicated VDDO supply pin |
| VDDOA–VDDOD | Output buffer supply rails | Four independent 1.8/2.5/3.3 V supplies for output banks (A: CLK0–1, B: CLK2–3, C: CLK4–5, D: CLK6–7) |
| VDD | Core logic supply | 2.5 V or 3.3 V core power; must be powered before or concurrently with all VDDO rails |
| SCL, SDA | I²C configuration interface | Standard bidirectional I²C bus (100/400 kbps); supports multiple devices on same bus via A0 pin |
| OEB | Output enable control | Active-low global enable; pulls all outputs to high-impedance when asserted |
| VC | VCXO control voltage input | 0 to VDD analog tuning input; enables ±240 ppm frequency adjustment with high linearity (±5%) |
| NC | No-connect | Pins 12, 13, 19, and 20 are no-connect; must be left floating or grounded per layout guidelines |
Key Features
| Feature | Design Value |
|---|---|
| 0 ppm frequency synthesis error | Each output achieves exact target frequency via fractional MultiSynth dividers - eliminates need for trimming or calibration |
| Glitchless frequency switching | Dynamic reconfiguration of output frequencies without clock interruption - essential for runtime clock scaling |
| Configurable spread spectrum | Per-output down-spread (–0.1% to –2.5%) or center-spread (±0.1% to ±1.5%) reduces EMI at system level |
| Static phase offset control | 333 ps/step resolution enables precise inter-clock alignment for DDR, video, or ADC sampling synchronization |
| Independent output voltage rails | Four VDDO banks allow simultaneous generation of 1.8 V, 2.5 V, and 3.3 V CMOS clocks - simplifies mixed-voltage board design |
Applications
| Audio/Video Timing | Networking Equipment |
|---|---|
Use Scenario: Generating synchronized pixel clocks (74.25 MHz), audio master clocks (24.576 MHz), and HDMI TMDS clocks (125 MHz) in AV receivers and set-top boxes. IC Role / Device Role / Timing Role: Single-chip replacement for multiple crystals and oscillators across disparate clock domains. Use Value: Eliminates board space occupied by 4–6 discrete timing components while maintaining <70 ps jitter compliance for HDMI 1.4 and AES3 interfaces. |
Use Scenario: Providing reference clocks for Ethernet PHYs (25 MHz), PCIe Gen 1 root complex (100 MHz), and packet processor SoCs (33.333 MHz) in residential gateways. IC Role / Device Role / Timing Role: PCIe Gen 1–compliant clock source with spread spectrum enabled to meet FCC Class B emissions limits. Use Value: Reduces EMI by >10 dB through per-output spread spectrum control without requiring additional filtering or shielding. |
| Laser Range Finding | Industrial Instrumentation |
Use Scenario: Delivering precisely phased trigger and sampling clocks (e.g., 28.322 MHz and 22.5792 MHz) for time-of-flight measurement in handheld laser rangefinders. IC Role / Device Role / Timing Role: High-resolution phase-aligned clock generator supporting sub-nanosecond timing accuracy. Use Value: Enables 1 mm distance resolution via 333 ps/step static phase offset control and <95 ps pk-pk period jitter. |
Use Scenario: Supplying isolated, low-jitter clocks to ADCs (48 MHz), DACs (27 MHz), and microcontrollers (33.333 MHz) in portable test equipment. IC Role / Device Role / Timing Role: Low-power, multi-rail clock hub with independent VDDO supplies for noise-sensitive analog and digital subsystems. Use Value: Achieves 22–27 mA core current (8 outputs active) and excellent PSRR - eliminates need for external LDOs or ferrite beads. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5351B-B-GM | Includes VCXO functionality with identical 8-output 20-QFN package and pinout; adds CLKIN input capability | Supports external reference synchronization (10–100 MHz CLKIN) - required for systems needing traceable timing or holdover operation | Select Si5351B-B-GM if VCXO tuning and external reference locking are both needed; SI5351A-B06884-GTR lacks CLKIN input |
| Si5351C-B-GM | Same 8-output 20-QFN package; adds CLKIN input and removes VC pin - synchronizes exclusively to external reference | Used where absolute frequency stability relative to system master clock is prioritized over voltage tuning flexibility | Choose Si5351C-B-GM for applications requiring deterministic phase relationship to a common system clock, not voltage-controlled drift compensation |
Compared with SI5351A-B06884-GTR, Si5351B-B-GM adds external clock input and retains VCXO tuning, while Si5351C-B-GM replaces VCXO with CLKIN-only synchronization - making SI5351A-B06884-GTR optimal for standalone, crystal-referenced, voltage-tunable clock generation without external reference dependency.
Availability
SI5351A-B06884-GTR is available at Aetrix Electronics and suitable for networking equipment, audio/video consumer electronics, and industrial instrumentation requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for SI5351A-B06884-GTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with emphasis on performance, integration, and reliability.
The SI5351A-B06884-GTR belongs to Skyworks' Si5351 family of I²C-programmable clock generators, designed specifically to replace multiple discrete timing components in cost- and space-constrained embedded systems while delivering low jitter and flexible frequency synthesis.
FAQ
What is the maximum number of unique frequencies above 112.5 MHz that SI5351A-B06884-GTR can generate simultaneously?
The SI5351A-B06884-GTR supports only two unique frequencies above 112.5 MHz at the same time - for example, 125 MHz on CLK0 and 130 MHz on CLK1. Additional outputs above this threshold must duplicate one of those two frequencies. This limitation arises from internal PLL bandwidth and divider resource allocation within the MultiSynth architecture, as specified in Skyworks Rev. 1.3 datasheet Table 7 footnote.
Does SI5351A-B06884-GTR support external clock input (CLKIN) in addition to the crystal reference?
No, SI5351A-B06884-GTR does not support external CLKIN. It is the Si5351A variant, which relies solely on the internal 25/27 MHz crystal oscillator (XA/XB) as its frequency reference. Only Si5351B and Si5351C variants include the CLKIN input pin; SI5351A-B06884-GTR lacks both CLKIN and associated input circuitry per functional block diagram and ordering guide.
What is the VCXO tuning range and linearity specification for SI5351A-B06884-GTR?
SI5351A-B06884-GTR does not include VCXO functionality. It is the Si5351A variant, which lacks the VC pin and associated voltage-controlled oscillator circuitry. VCXO capability is exclusive to Si5351B and Si5351C variants. Therefore, SI5351A-B06884-GTR provides only free-running, crystal-referenced clock generation without voltage tuning.
Can SI5351A-B06884-GTR generate HCSL-compatible output swing?
Yes, SI5351A-B06884-GTR supports HCSL-compatible output swing through programmable drive strength and termination settings. When configured with 50 Ω output impedance and appropriate VDDO (typically 1.8 V), its CMOS outputs meet HCSL voltage thresholds (VOH ≥ 0.75 V, VOL ≤ 0.25 V) and edge rate requirements, as confirmed in Skyworks Application Note AN551 and Si5351A/B/C-B datasheet Section 4.3.
What are the supported crystal load capacitance values for SI5351A-B06884-GTR?
SI5351A-B06884-GTR supports internal crystal load capacitance values of 0 pF, 6 pF, 8 pF, or 10 pF, selectable via register 183 bits 7:6. Crystals requiring 12 pF load capacitance may use the internal 10 pF setting plus ≤2 pF total external capacitance (e.g., 4 pF capacitors on XA and XB), as detailed in Skyworks Si5351A/B/C-B datasheet Table 8 and AN551.
SI5351A-B06884-GTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- *
- Package/Case:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- -
- PLL:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Divider/Multiplier:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- -
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
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SI5351A-B06884-GTR FAQ
1.How can I place an order for SI5351A-B06884-GTR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5351A-B06884-GTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5351A-B06884-GTR reliable?
The price and inventory of SI5351A-B06884-GTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5351A-B06884-GTR is usually 5 days.
3.What payment methods are accepted for SI5351A-B06884-GTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5351A-B06884-GTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5351A-B06884-GTR?
SI5351A-B06884-GTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5351A-B06884-GTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5351A-B06884-GTR?
For technical support, including SI5351A-B06884-GTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5351A-B06884-GTR requirements.
6.How does Aetrix verify that SI5351A-B06884-GTR is sourced from the original manufacturer or authorized distributors?
All SI5351A-B06884-GTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5351A-B06884-GTR meets industry standards.
7.What is the process for return or replacement of SI5351A-B06884-GTR?
All SI5351A-B06884-GTR units undergo pre-shipment inspection (PSI). If there is an issue with SI5351A-B06884-GTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5351A-B06884-GTR part is unused and in its original packaging.
Return procedure for SI5351A-B06884-GTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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