Skyworks Solutions Inc. SI5351C-B06050-GM

Overview

SI5351C-B06050-GM from Skyworks Solutions is an I²C-programmable, 4-output CMOS clock generator with external reference (CLKIN) synchronization capability, integrated PLL/VCXO architecture, 0 ppm frequency synthesis error up to 200 MHz, <70 ps pk-pk period jitter, and independent 1.8/2.5/3.3 V output supply rails. It replaces crystals, crystal oscillators, and synchronous clock sources in residential gateways and networking equipment.

For engineers reviewing the SI5351C-B06050-GM datasheet, SI5351C-B06050-GM pinout, SI5351C-B06050-GM application, or SI5351C-B06050-GM equivalent, key selection criteria include CLKIN-synchronized multi-domain clock generation, VCXO-free operation, programmable spread spectrum per output, and 4-output 16-QFN (3×3 mm) package compatibility with PCIe Gen 1 timing requirements.

Technical Context

The SI5351C-B06050-GM uses dual PLLs (PLLA and PLLB) with a crosspoint switch enabling either PLL to lock to CLKIN (10–100 MHz) or the internal 25/27 MHz crystal oscillator. Its MultiSynth fractional dividers provide independent frequency synthesis per output with static phase offset support and glitchless frequency changes.

It implements a dedicated input stage for CLKIN reference routing, two-stage synthesis (PLL multiplication followed by high-resolution fractional division), and configurable output drive strength with rise/fall time control. The device supports HCSL-compatible swing and operates with separate core (2.5/3.3 V) and output (1.8/2.5/3.3 V) supply domains.

Key Specifications

Pinout & Package

The SI5351C-B06050-GM is housed in a 16-pin QFN package (3 × 3 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5351C 16-QFN specification (Rev. 1.3, Section 10.6).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5351B-B-GM1 and Si5351A-B-GM1, the SI5351C-B06050-GM uniquely supports external reference locking without VCXO complexity-enabling deterministic timing in distributed systems while retaining full I²C configurability and 4-output flexibility in the same compact 16-QFN footprint.

Availability

SI5351C-B06050-GM is available at Aetrix Electronics and suitable for residential gateways, networking equipment, laser range finders, and audio/video equipment requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5351C-B06050-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5351 family is designed for flexible, software-configurable clock generation in cost-sensitive, space-constrained applications-replacing multiple discrete timing components with a single I²C-programmable IC supporting crystal, VCXO, and external reference modes.

FAQ

What reference inputs does the SI5351C-B06050-GM support?

The SI5351C-B06050-GM supports both an internal 25/27 MHz crystal oscillator (via XA/XB pins) and an external 10–100 MHz clock input (CLKIN). Unlike the Si5351A and Si5351B variants, it does not include a VCXO and relies solely on CLKIN for synchronization-making it ideal for systems with a stable master reference clock. The SI5351C-B06050-GM uses these references to drive its dual PLL architecture for precise, low-jitter output synthesis.

How many outputs does the SI5351C-B06050-GM provide, and what are their electrical characteristics?

The SI5351C-B06050-GM provides four CMOS clock outputs (CLK0–CLK3) in a 16-pin QFN package. Each output supports 2.5 kHz–200 MHz frequencies, 45–55% duty cycle (below 160 MHz), <1.5 ns rise/fall time (20–80%, CL = 5 pF), and programmable drive strength. Outputs are powered by independent VDDO rails (VDDOA–VDDOD), allowing mixed-voltage interfacing (1.8/2.5/3.3 V) without external level shifters-critical for modern heterogeneous SoC designs using the SI5351C-B06050-GM.

Does the SI5351C-B06050-GM support spread spectrum clocking, and how is it configured?

Yes, the SI5351C-B06050-GM supports per-output spread spectrum clocking (SSC) with selectable down-spread (–0.1% to –2.5%) or center-spread (±0.1% to ±1.5%) modulation at 31.5 kHz. SSC is configured independently for each output via I²C register writes-no hardware changes required. This feature reduces electromagnetic interference (EMI) peaks in sensitive applications like residential gateways and audio/video equipment, directly improving FCC/CE compliance margins without altering PCB layout or adding filtering components to the SI5351C-B06050-GM design.

What is the power supply configuration for the SI5351C-B06050-GM?

The SI5351C-B06050-GM requires two independent supply domains: core VDD (2.25–2.75 V or 3.0–3.6 V) for internal logic and PLLs, and four output-specific VDDO rails (VDDOA–VDDOD, each 1.71–1.89 V, 2.25–2.75 V, or 3.0–3.6 V) for clock buffers. Power sequencing mandates that all VDDOx supplies be powered before or simultaneously with VDD. This architecture enables the SI5351C-B06050-GM to drive mixed-voltage interfaces-such as 1.8 V FPGAs and 3.3 V peripherals-from a single chip while maintaining excellent PSRR and eliminating need for external LDOs or filters.

Can the SI5351C-B06050-GM generate frequencies above 112.5 MHz, and what are the limitations?

Yes, the SI5351C-B06050-GM can generate frequencies up to 200 MHz, but only two unique frequencies above 112.5 MHz may be active simultaneously (e.g., 125 MHz on CLK0 and 130 MHz on CLK1). Duplicate frequencies above 112.5 MHz are permitted across multiple outputs (e.g., 125 MHz on CLK0–CLK3). This limitation arises from internal PLL bandwidth and MultiSynth divider resolution constraints-not from package or thermal limits. Designers using the SI5351C-B06050-GM should plan frequency assignments accordingly to avoid configuration errors during I²C initialization.