Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5351C-B06896-GM

Name: SI5351C-B06896-GM
Brand: Skyworks Solutions Inc.
SKU: SI5351C-B06896-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5351C-B06896-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5351C-B06896-GM.pdf

Description:: I2C PROG, ANY FREQUENCY, ANY OUT

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,653

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5351C-B06896-GM from Skyworks Solutions is an I²C-programmable CMOS clock generator with integrated VCXO architecture, synchronized to an external reference clock (CLKIN). It delivers up to four independent output frequencies from 2.5 kHz to 200 MHz with 0 ppm synthesis error, low period jitter (<70 ps pk-pk), and configurable output drive voltage (1.8/2.5/3.3 V). It replaces crystals, crystal oscillators, and VCXOs in residential gateways and networking equipment.

For engineers reviewing the SI5351C-B06896-GM datasheet, SI5351C-B06896-GM pinout, SI5351C-B06896-GM application, or SI5351C-B06896-GM equivalent, key selection criteria include CLKIN synchronization capability, 4-output QFN-16 package, VCXO-free operation (vs. Si5351B), I²C programmability, and support for HCSL-compatible swing and spread spectrum modulation.

Technical Context

The SI5351C-B06896-GM uses a dual-PLL architecture where PLLA and PLLB accept either the internal 25/27 MHz crystal oscillator or an external 10–100 MHz CLKIN reference. Its MultiSynth fractional dividers provide per-output frequency synthesis with static phase offset control and glitchless frequency changes.

Unlike the Si5351B, the SI5351C omits the VC pin and relies solely on CLKIN for synchronization-enabling deterministic timing alignment across multiple clock domains without analog tuning voltage. Output buffers support independent VDDO rails (1.8/2.5/3.3 V) and programmable rise/fall times.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	4 independent CMOS clock outputs (CLK0–CLK3)
Frequency range	2.5 kHz to 200 MHz per output; only two unique frequencies >112.5 MHz simultaneously
Reference input	External CLKIN (10–100 MHz) or internal 25/27 MHz crystal - no VC pin
Period jitter	<70 ps pk-pk (typical, all outputs active, default drive strength)
Supply voltages	Core VDD: 2.25–3.6 V; Output VDDO: 1.71–3.6 V (per bank)
I²C interface	Standard/Fast mode (100/400 kbps); supports register-based configuration and real-time reprogramming
Spread spectrum	Selectable per output: down-spread (–0.1% to –2.5%) or center-spread (±0.1% to ±1.5%) at 31.5 kHz

Pinout & Package

SI5351C-B06896-GM is housed in a 16-pin QFN package (3 mm × 3 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5351C 16-QFN pinout specification (Rev. 1.3, Section 10.6).

Pin/Terminal	Circuit Role	Design Meaning
CLK0–CLK3	CMOS clock outputs	Four configurable frequency outputs; each with independent MultiSynth divider, drive strength, and spread spectrum control
VDDOA–VDDOD	Output buffer supply rails	Independent 1.8/2.5/3.3 V supplies per output pair - enables mixed-voltage system interfacing
SCL, SDA	I²C serial interface	Two-wire bus for register writes, configuration loading, and status reads; supports multi-device addressing via A0 pin
OEB	Output enable bar	Active-low global enable; asserts high-impedance state on all outputs when pulled high
CLKIN	External reference input	Accepts 10–100 MHz single-ended clock; used as PLL reference instead of internal crystal or VCXO
XA, XB	Crystal oscillator inputs	Connects to 25 or 27 MHz AT-cut crystal; internal load capacitance selectable (0/6/8/10 pF)
VDD, GND	Core power and ground	2.25–3.6 V core supply; decoupling required per layout guidelines (Section 7.1)
A0	I²C address select	Configures LSB of 7-bit I²C address (0x60 or 0x61); enables up to two devices on same bus

Key Features

Feature	Design Value
CLKIN-synchronized synthesis	Enables deterministic phase relationships between outputs and system master clock - critical for PCIe Gen 1 and synchronous Ethernet applications
Per-output spread spectrum	Reduces EMI by modulating individual clock frequencies - avoids correlated noise peaks across multiple outputs
Static phase offset control	Allows precise inter-output skew adjustment (333 ps/step resolution) for timing-critical interfaces like DDR or MIPI
Glitchless frequency switching	Ensures uninterrupted clock delivery during dynamic reconfiguration - eliminates system resets or data loss
HCSL-compatible swing	Configurable output drive supports HCSL-level signaling (≈0.8 Vpp) without external termination - simplifies high-speed SerDes clocking

Applications

Residential Gateway Timing	Networking Switch Clocking
Use Scenario: Provides synchronized clocks for CPU, Ethernet PHYs, and Wi-Fi SoC in broadband home routers. IC Role / Device Role / Timing Role: Central clock source distributing 25 MHz, 125 MHz, and 156.25 MHz with sub-nanosecond skew control. Use Value: Eliminates need for three discrete oscillators while maintaining IEEE 1588 PTP timing accuracy via CLKIN lock to upstream DSLAM clock.	Use Scenario: Generates reference clocks for multiple 1G/2.5G Ethernet ports and management MCU in managed Layer 2 switches. IC Role / Device Role / Timing Role: Four-output clock generator delivering 25 MHz (PHY), 125 MHz (RGMII), 156.25 MHz (SFP+), and 33.333 MHz (MCU) from single CLKIN reference. Use Value: Reduces BOM count and PCB area vs. discrete XO solutions; spread spectrum on RGMII clock lowers radiated emissions to meet FCC Class B limits.
Laser Range Finder Synchronization	Audio/Video Equipment Clocking
Use Scenario: Coordinates time-of-flight measurement circuitry, ADC sampling, and FPGA processing in handheld laser distance meters. IC Role / Device Role / Timing Role: Delivers 48 MHz (FPGA logic), 100 MHz (ADC sampling), and 24.576 MHz (audio codec) with static phase offsets calibrated for pipeline latency matching. Use Value: Achieves <±1 ns inter-clock skew tolerance required for picosecond-resolution time-of-flight calculation - unattainable with free-running crystals.	Use Scenario: Supplies pixel clock, audio master clock, and HDMI TMDS clock in AV receivers and soundbars. IC Role / Device Role / Timing Role: Generates 74.25 MHz (HDMI), 48 MHz (USB audio), 24.576 MHz (I²S), and 33.333 MHz (video processor) from single 27 MHz crystal. Use Value: Enables simultaneous multi-format output (HDMI + optical SPDIF + analog) without clock domain crossing artifacts or audible jitter-induced distortion.

Residential Gateway Timing

Networking Switch Clocking

Use Scenario: Provides synchronized clocks for CPU, Ethernet PHYs, and Wi-Fi SoC in broadband home routers.

IC Role / Device Role / Timing Role: Central clock source distributing 25 MHz, 125 MHz, and 156.25 MHz with sub-nanosecond skew control.

Use Value: Eliminates need for three discrete oscillators while maintaining IEEE 1588 PTP timing accuracy via CLKIN lock to upstream DSLAM clock.

Use Scenario: Generates reference clocks for multiple 1G/2.5G Ethernet ports and management MCU in managed Layer 2 switches.

IC Role / Device Role / Timing Role: Four-output clock generator delivering 25 MHz (PHY), 125 MHz (RGMII), 156.25 MHz (SFP+), and 33.333 MHz (MCU) from single CLKIN reference.

Use Value: Reduces BOM count and PCB area vs. discrete XO solutions; spread spectrum on RGMII clock lowers radiated emissions to meet FCC Class B limits.

Laser Range Finder Synchronization

Audio/Video Equipment Clocking

Use Scenario: Coordinates time-of-flight measurement circuitry, ADC sampling, and FPGA processing in handheld laser distance meters.

IC Role / Device Role / Timing Role: Delivers 48 MHz (FPGA logic), 100 MHz (ADC sampling), and 24.576 MHz (audio codec) with static phase offsets calibrated for pipeline latency matching.

Use Value: Achieves <±1 ns inter-clock skew tolerance required for picosecond-resolution time-of-flight calculation - unattainable with free-running crystals.

Use Scenario: Supplies pixel clock, audio master clock, and HDMI TMDS clock in AV receivers and soundbars.

IC Role / Device Role / Timing Role: Generates 74.25 MHz (HDMI), 48 MHz (USB audio), 24.576 MHz (I²S), and 33.333 MHz (video processor) from single 27 MHz crystal.

Use Value: Enables simultaneous multi-format output (HDMI + optical SPDIF + analog) without clock domain crossing artifacts or audible jitter-induced distortion.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generation applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5351B-B-GM1	Includes VC pin for analog VCXO tuning; same 4-output QFN-16 package and I²C interface	Required where system-level frequency pulling (e.g., telecom clock recovery) is needed instead of fixed CLKIN lock	Select Si5351B-B-GM1 if voltage-controlled frequency adjustment is mandatory; otherwise SI5351C-B06896-GM offers simpler power and layout with no VC filtering
Si5341-A-GM	Higher-performance 10-output clock generator with JESD204B compliance, lower jitter (35 ps pk-pk), and integrated jitter cleaner	Targeted at high-speed data converters and RF sampling systems requiring sub-100 fs jitter	Choose Si5341-A-GM only when jitter budget is <50 ps pk-pk or >8 outputs are needed; SI5351C-B06896-GM remains optimal for cost-sensitive 4-output applications

Compared with Si5351B-B-GM1, SI5351C-B06896-GM removes VC complexity and reduces external component count, while compared with Si5341-A-GM it trades higher integration and jitter performance for lower unit cost and smaller footprint - making it ideal for mid-tier networking and consumer timing.

Availability

SI5351C-B06896-GM is available at Aetrix Electronics and suitable for residential gateways, networking switches, and laser range finders requiring stable component supply, long-term lifecycle support, and consistent parametric performance across temperature (–40°C to +85°C).

Supply support for SI5351C-B06896-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5351 family was designed to replace discrete timing components in cost-sensitive, space-constrained applications - delivering programmable flexibility without sacrificing jitter performance or reliability.

FAQ

What reference clock sources does the SI5351C-B06896-GM support?

The SI5351C-B06896-GM supports two reference sources: an internal 25 or 27 MHz crystal connected to XA/XB pins, or an external 10–100 MHz single-ended clock applied to the CLKIN pin. Unlike the Si5351B, it does not support VCXO tuning via a VC pin - synchronization is strictly digital and clock-domain based. This makes SI5351C-B06896-GM ideal for systems where master clock distribution is already established.

How many unique frequencies above 112.5 MHz can the SI5351C-B06896-GM generate simultaneously?

The SI5351C-B06896-GM can generate only two unique frequencies above 112.5 MHz at the same time - for example, 125 MHz on CLK0 and 133.333 MHz on CLK1. Additional outputs may replicate those two frequencies (e.g., 125 MHz on CLK2 and CLK3), but no third distinct frequency >112.5 MHz is permitted. This constraint arises from internal PLL bandwidth and MultiSynth divider resolution limits documented in Skyworks Rev. 1.3 datasheet Table 7.

Does the SI5351C-B06896-GM require external load capacitors for its crystal connection?

The SI5351C-B06896-GM integrates programmable internal load capacitance (0, 6, 8, or 10 pF) and typically requires no external crystal load capacitors. Only crystals specifying ≥12 pF load capacitance need ≤2 pF additional external capacitance (e.g., 4 pF total split across XA and XB). This simplifies layout and improves yield versus traditional crystal oscillator designs - a key advantage of the SI5351C-B06896-GM in high-volume consumer applications.

Can the SI5351C-B06896-GM generate HCSL-compatible output levels?

Yes, the SI5351C-B06896-GM supports HCSL-compatible swing through programmable output drive strength and termination control. When configured with 50 Ω output impedance and appropriate VDDO (e.g., 1.8 V), it delivers ≈0.8 Vpp differential-like swing into 50 Ω loads - meeting HCSL electrical specifications for interfaces such as PCIe Gen 1 and SATA. This capability is confirmed in Skyworks Application Note AN551 and Section 4.3 of the SI5351C-B06896-GM datasheet.

Is the SI5351C-B06896-GM pin-compatible with other Si5351 variants in the 16-QFN package?

Yes, the SI5351C-B06896-GM shares identical pinout and footprint with Si5351A-B-GM1 and Si5351B-B-GM1 in the 16-QFN (3×3 mm) package, as defined in Skyworks datasheet Section 10.4–10.6. All three variants use the same CLK0–CLK3, VDDOA–VDDOD, SCL/SDA, OEB, CLKIN, XA/XB, VDD, GND, and A0 pin assignments. However, functional differences exist - notably the absence of the VC pin in SI5351C-B06896-GM - so firmware and schematic design must reflect the C-variant's CLKIN-only synchronization model.

SI5351C-B06896-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Strip

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5351C-B06896-GM FAQ

1.How can I place an order for SI5351C-B06896-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5351C-B06896-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5351C-B06896-GM reliable?

The price and inventory of SI5351C-B06896-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5351C-B06896-GM is usually 5 days.

3.What payment methods are accepted for SI5351C-B06896-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5351C-B06896-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5351C-B06896-GM?

SI5351C-B06896-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5351C-B06896-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5351C-B06896-GM?

For technical support, including SI5351C-B06896-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5351C-B06896-GM requirements.

6.How does Aetrix verify that SI5351C-B06896-GM is sourced from the original manufacturer or authorized distributors?

All SI5351C-B06896-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5351C-B06896-GM meets industry standards.

7.What is the process for return or replacement of SI5351C-B06896-GM?

All SI5351C-B06896-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5351C-B06896-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5351C-B06896-GM part is unused and in its original packaging.

Return procedure for SI5351C-B06896-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…