Skyworks Solutions Inc. SI5356A-B-GMR

Overview

SI5356A-B-GMR from Skyworks Solutions is an I²C-programmable, quad-frequency, 8-output CMOS clock generator synthesizing four independent non-integer-related frequencies from 1 to 200 MHz per bank. It uses patented MultiSynth fractional-N PLL architecture with 0 ppm synthesis error, supports 1.8/2.5/3.3 V core and per-bank VDDO supplies, and delivers low jitter (50 ps pk-pk typical) for timing-critical networking and computing systems.

For engineers reviewing the SI5356A-B-GMR datasheet, SI5356A-B-GMR pinout, SI5356A-B-GMR application, or SI5356A-B-GMR equivalent, this device enables single-chip replacement of multiple crystal oscillators and discrete clock ICs in multi-clock domain systems requiring precise phase alignment, spread spectrum control, and field-reprogrammable frequency plans.

Technical Context

The SI5356A-B-GMR implements a single high-frequency VCO feeding four independent MultiSynth fractional dividers-each with dynamic phase error correction-to guarantee 0 ppm frequency accuracy across all eight outputs. Its architecture eliminates integer-related constraints, enabling arbitrary combinations of 1–200 MHz outputs without reference clock changes.

It accepts either a 25/27 MHz fundamental-mode crystal (XA/XB) or a 5–200 MHz CMOS reference clock (CLKIN), supports per-bank output voltage selection (1.8/2.5/3.3 V), and integrates programmable phase adjustment (<20 ps error, ±45 ns range) and triple-A spread spectrum (any clock, any frequency, any spread amount).

Key Specifications

Pinout & Package

SI5356A-B-GMR is housed in a 4×4 mm, 24-pin QFN package with exposed thermal pad (RoHS-compliant, JEDEC J-STD-020 Pb-free profile). Pin functions are validated per Skyworks Rev. 1.4 datasheet (November 2021), including dedicated crystal inputs (XA/XB), reference clock input (CLKIN), interrupt (INTR), output enable (OEB), and I²C interface (SCL/SDA).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5356B-B-GMR, SI5356A-B-GMR provides full in-system programmability and blank NVM for flexible deployment; versus LMK04832RHAR, it trades ultra-low jitter for smaller footprint, lower power, and simpler board design-making it optimal for cost-sensitive, space-constrained embedded timing.

Availability

SI5356A-B-GMR is available at Aetrix Electronics and suitable for printers, audio/video equipment, DSLAM systems, and servers requiring stable component supply, long-term lifecycle support, and consistent electrical performance across temperature and voltage.

Supply support for SI5356A-B-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog technologies.

The Si5356 product line was designed to simplify timing architectures in high-density digital systems by replacing multiple discrete clocks with a single, software-configurable, low-jitter clock generator-targeting networking, computing, and consumer electronics.

FAQ

What is the default power-up behavior of the SI5356A-B-GMR?

The SI5356A-B-GMR boots from its one-time programmable (OTP) NVM, which contains a factory-default configuration. Since SI5356A-B-GMR is a blank part, this default config produces no output clocks until programmed via I²C. Users must write a valid register map to RAM using ClockBuilder Desktop or custom firmware before outputs become active. The SI5356A-B-GMR does not generate clocks at power-up unless explicitly configured.

Can the SI5356A-B-GMR generate different frequencies on CLK0 and CLK1?

No-the SI5356A-B-GMR groups outputs into four fixed banks: CLK0/CLK1 (Bank A), CLK2/CLK3 (Bank B), CLK4/CLK5 (Bank C), and CLK6/CLK7 (Bank D). Within each bank, both outputs must run at the identical frequency. However, Bank A can run at 125 MHz while Bank B runs at 100 MHz, and so on. So CLK0 and CLK1 always share frequency, but SI5356A-B-GMR supports four independent frequencies across its eight outputs.

Does the SI5356A-B-GMR require external loop filter components?

No-the SI5356A-B-GMR integrates all PLL loop filter components internally. Its single PLL architecture with patented MultiSynth fractional dividers eliminates the need for external resistors, capacitors, or inductors typically required in multi-PLL clock generators. This simplifies layout, reduces BOM count, and improves reliability compared to traditional discrete PLL designs.

How is spread spectrum applied on the SI5356A-B-GMR?

Spread spectrum on the SI5356A-B-GMR is implemented as down-spread only, configurable per output bank via I²C registers. It modulates the output frequency with a user-defined center frequency, spread rate (0.1–5 kHz), and spread amount (0.1–4.0%). The SI5356A-B-GMR's "triple-A" capability means any enabled output, at any synthesized frequency, can have independently set spread parameters-without affecting other banks or requiring hardware changes.

What is the maximum output load capacitance supported by the SI5356A-B-GMR?

The SI5356A-B-GMR specifies a maximum output load capacitance of 15 pF per clock output, as defined in Table 3 of the Rev. 1.4 datasheet. Driving loads beyond 15 pF may degrade rise/fall times (max 2.0 ns for 20–80% VDD at CL = 15 pF) and increase jitter. For heavier loads, external buffering or reduced trace length/impedance is recommended. The SI5356A-B-GMR's 50 Ω output impedance is optimized for 50 Ω transmission lines with ≤15 pF net load.