Skyworks Solutions Inc. SI5360A-A-GM

Overview

SI5360A-A-GM from Skyworks Solutions is an 18-output, any-frequency clock generator featuring fifth-generation DSPLL® and MultiSynth™ architectures, delivering ultra-low phase jitter of 55 fs RMS (integer mode) and 100 fs RMS (fractional mode). It supports up to six differential or single-ended inputs (30.72 MHz–750 MHz), 18 programmable outputs (8 kHz–1.3 GHz differential), and operates across –40 to +95 °C ambient. It serves as a core timing engine in 112G/224G PAM4 SerDes and high-speed optical transceivers.

For engineers reviewing the SI5360A-A-GM datasheet, SI5360A-A-GM pinout, SI5360A-A-GM application, or SI5360A-A-GM equivalent, key selection considerations include its dual-MultiSynth fractional synthesis capability, per-output programmable delay and slew rate control (OUT16/OUT17), configurable LVDS/LVPECL/CML/HCSL/LVCMOS output formats, and factory-programmable NVM configuration via ClockBuilder Pro.

Technical Context

The SI5360A-A-GM integrates one DSPLL with two independent MultiSynth blocks (NA/NB), enabling simultaneous integer and fractional frequency synthesis paths. Its crosspoint switch routes any synthesized frequency-derived from Q dividers (integer-only) or NA/NB dividers (integer/fractional)-to any of 18 outputs, with R dividers fine-tuning MultiSynth-derived outputs.

Input selection is software-controlled via SPI/I²C; supported references include external crystal (48–61.44 MHz on XA/XB), differential clocks (30.72 MHz–750 MHz), or LVCMOS (30.72 MHz–250 MHz). Output banks (VDDO1–VDDO7) are independently powered at 3.3 V/2.5 V/1.8 V, enabling mixed-voltage signaling across domains without level shifters.

Key Specifications

Pinout & Package

SI5360A-A-GM uses a 72-lead QFN package (10 × 10 mm) with exposed thermal pad (GND PAD) requiring solder connection to PCB ground plane for thermal and EMI performance. Power supply pins are segregated by function: VDDIN (input buffers), VDDA/VDD18 (core analog/digital), VDDIO (serial interface), VDDXO (reference), and seven VDDOx banks (output drivers).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with SI5360A-A-GM, the Si5362A-A-GM adds EEPROM-based configuration retention and finer DCO steps, while the LTC6957IUF-3#PBF trades channel count, synthesis flexibility, and jitter performance for reduced component count and lower cost in less demanding timing roles.

Availability

SI5360A-A-GM is available at Aetrix Electronics and suitable for 112G SerDes clocking, OTN line card timing, and Synchronous Ethernet infrastructure requiring stable component supply, long-term lifecycle assurance, and consistent parametric performance across production lots.

Supply support for SI5360A-A-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The SI5360A-A-GM belongs to Skyworks' Si536x family of ultra-low-jitter clock generators, engineered specifically for next-generation optical networking, AI/ML infrastructure, and coherent transmission systems demanding sub-100 fs jitter and multi-domain frequency agility.

FAQ

What is the maximum differential output frequency supported by the SI5360A-A-GM?

The SI5360A-A-GM supports differential output frequencies up to 1.3 GHz. This capability enables direct clocking of 112G PAM4 SerDes CDRs without intermediate fanout or frequency multiplication stages. The 1.3 GHz limit applies to LVDS, LVPECL, S-LVDS, CML, and HCSL output formats. For LVCMOS outputs, the maximum frequency is 250 MHz. All output frequencies are programmable via ClockBuilder Pro using integer Q or fractional NA/NB dividers.

Does the SI5360A-A-GM require an external crystal, or can it accept other reference inputs?

The SI5360A-A-GM supports multiple reference options: an external crystal (48–61.44 MHz) connected to XA/XB pins, a differential or single-ended clock (30.72 MHz–750 MHz) on IN0–IN3, or a crystal oscillator (XO) on XO_IN/XO_INb (30.72 MHz–983.04 MHz). The device does not require an external crystal - it can operate with any of these sources. Crystal use is recommended for lowest jitter; XO inputs are viable when ultra-low phase noise is provided externally.

How many power supply domains does the SI5360A-A-GM have, and what do they serve?

The SI5360A-A-GM has seven distinct power supply domains: VDDIN (input buffers), VDDA/VDD18 (analog/digital core), VDDIO (serial interface), VDDXO (reference circuit), and VDDO1–VDDO7 (seven output driver banks). Each VDDOx powers a specific group of outputs (e.g., VDDO1 → OUT0–OUT3), allowing independent voltage selection (3.3 V/2.5 V/1.8 V) per bank to match downstream logic families and minimize noise coupling between domains.

Can the SI5360A-A-GM generate different output formats simultaneously, such as LVPECL and LVCMOS?

Yes, the SI5360A-A-GM can generate multiple output formats simultaneously. Outputs can be individually configured as LVDS, S-LVDS, LVPECL, CML, HCSL, or LVCMOS (3.3 V/2.5 V/1.8 V) via ClockBuilder Pro. For example, OUT0–OUT3 (powered by VDDO1) may be set to LVPECL, while OUT16–OUT17 (VDDO7) operate as slew-rate-limited LVCMOS. Format selection is per-output and persists after power-up when stored in NVM.

Is the SI5360A-A-GM pin-compatible with other devices in the Si536x family?

Yes, the SI5360A-A-GM is pin-compatible with the Si5361/62/63 jitter attenuators and Si5401/02/03 IEEE 1588 PTP synchronizers. This allows drop-in replacement in existing PCB layouts when upgrading from jitter attenuation to full clock generation functionality or adding PTP-aware timing. Pin compatibility covers all 72 QFN pads, including power, I/O, and control signals - no board redesign is required for migration within this footprint family.