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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5362B-A15684-GMR

Name: SI5362B-A15684-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5362B-A15684-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5362B-A15684-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 72-VFQFN Exposed Pad

Datasheet:: SI5362B-A15684-GMR.pdf

Description:: Linear IC's

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Product details

Overview

SI5362B-A15684-GMR from Skyworks Solutions is a dual-DSPLL, zero-MultiSynth jitter attenuator/clock multiplier delivering ultra-low phase jitter (<55 fs RMS typ) for 112G/224G SerDes and coherent optics clocking. It supports 18 differential outputs up to 1.3 GHz (Q-divider), six differential/single-ended inputs, and operates across –40 to +95 °C ambient with 72-QFN 10×10 mm packaging.

For engineers reviewing the SI5362B-A15684-GMR datasheet, SI5362B-A15684-GMR pinout, SI5362B-A15684-GMR application, or SI5362B-A15684-GMR equivalent, key selection factors include DSPLLA/B independent synchronization capability, hitless switching with ≤35 ps phase transient, programmable loop bandwidth (20 Hz–4 kHz), output skew ±50 ps, and support for LVDS/LVPECL/CML/HCSL/LVCMOS formats with per-output voltage supply control.

Technical Context

The SI5362B-A15684-GMR implements two independent DSPLLs (DSPLLA and DSPLLB) with no MultiSynth blocks-enabling fully separate input-to-output frequency synthesis paths. Each DSPLL supports integer Q-dividers (8 kHz–1.3 GHz) and fractional NA/NB dividers (8 kHz–650 MHz), with independent loop bandwidth programming (20 Hz–4 kHz) and Zero Delay Mode (ZDM) for deterministic latency.

It features enhanced hitless switching between synchronous inputs with ≤35 ps typical phase transient, automatic free-run/holdover/locked mode transitions, and full status monitoring (LOS, OOF, PHMON, FLOL, PLOL). Input monitoring includes loss-of-signal detection and frequency lock validation per DSPLL.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase jitter (RMS)	<55 fs typ (12 kHz–20 MHz); enables compliance with PCIe Gen6 (100 fs RMS limit) and 224G SerDes timing budgets
Output count & type	18 differential or 36 single-ended outputs; supports mixed-format routing (LVDS, LVPECL, CML, HCSL, LVCMOS)
Max output frequency	1.3 GHz (Q-divider); 650 MHz (fractional NA/NB); sufficient for 112G PAM4 reference clocks and OTN line rates
Input flexibility	Up to six differential or single-ended inputs; 8 kHz–1 GHz (diff), 8 kHz–250 MHz (LVCMOS); accommodates multiple network sync sources
DSPLL architecture	Two independent DSPLLs (DSPLLA + DSPLLB); enables dual-reference redundancy and independent jitter cleanup paths
Hitless switching	≤35 ps typical phase transient; maintains SerDes lock during input failover without link reset
Operating temperature	–40 to +95 °C ambient; validated for telecom line cards and datacenter switch modules

Pinout & Package

Package: 72-lead QFN, 10 × 10 mm, 0.5 mm pitch, exposed thermal pad. RoHS-compliant, Pb-free.

Pin/Terminal	Circuit Role	Design Meaning
VDDIN, VDDA, VDD18, VDDIO, VDDXO, VDDO	Supply rails	Dedicated power domains: core (1.8 V), analog (3.3 V), XO (3.3 V), I/O (1.8/2.5/3.3 V), output buffers (1.8/2.5/3.3 V)-enables noise isolation and voltage optimization per function
IN0–IN5 / IN0b–IN5b	Differential clock inputs	Accept AC-coupled LVDS/LVPECL/CML (8 kHz–1 GHz); support automatic input format detection and LOS monitoring
XO_IN / XO_INb	Crystal oscillator reference input	Differential interface for 48–61.44 MHz XTAL; internal termination eliminates external resistors
OUT0–OUT17	Differential clock outputs	18 configurable outputs with per-pin format, amplitude, and slew control; OUT0–15 optimized for >500 MHz operation
SCLK, SDA/SDIO, A0/CSb, RSTb	Serial interface & control	I²C or SPI (3-/4-wire) configuration; hardware reset with glitch immunity; address select for multi-device buses
GPIO[0:3]	General-purpose I/O	Programmable as status indicators (e.g., LOL, LOS) or control inputs (e.g., manual clock switch trigger)

Key Features

Feature	Design Value
Dual independent DSPLLs	Enables fully isolated jitter attenuation paths-one for primary sync source, one for backup-critical for SyncE and IEEE 1588 boundary clocks
Zero Delay Mode (ZDM)	Guarantees deterministic input-to-output delay (±100 ps) across temperature and voltage; essential for phase-sensitive applications like coherent optics
Enhanced hitless switching	Automated or manual input switching with ≤35 ps phase transient-prevents SerDes retraining in 100G+ systems
Per-output voltage and format control	Each output supports independent VDDO (1.8/2.5/3.3 V) and format (LVDS/LVPECL/CML/HCSL/LVCMOS); simplifies board-level signal integrity tuning
In-circuit NVM programming	Factory- or field-programmable non-volatile memory enables known-frequency power-up without host MCU initialization

Applications

56G/112G/224G PAM4 SerDes Clocking	OTN Muxponders and Transponders
Use Scenario: High-speed optical interconnects requiring sub-100 fs jitter for 224G PAM4 signaling in AI/ML clusters and cloud infrastructure. IC Role / Device Role / Timing Role: Jitter attenuator generating clean, low-phase-noise reference clocks for SerDes PHYs with deterministic latency via ZDM. Use Value: Enables PCIe Gen6 and CEI-112G compliance with <55 fs RMS jitter and ≤35 ps hitless switch transient-reducing bit error rate in long-reach links.	Use Scenario: Aggregating multiple client-side OTN signals into line-side 400G/800G wavelengths in metro/core transport nodes. IC Role / Device Role / Timing Role: Dual-DSPLL clock multiplier providing synchronized, jitter-cleaned clocks for OTN framers and FEC engines. Use Value: Independent DSPLLA/B paths allow primary/backup reference sourcing with seamless failover-meeting ITU-T G.8262 ePRTC holdover stability requirements.
Synchronous Ethernet Line Cards	100G/200G/400G Optical Transceivers
Use Scenario: Timing distribution on high-density 400G line cards where EEC Option 1/2 compliance and phase alignment across 16+ ports are mandatory. IC Role / Device Role / Timing Role: Stratum 3E-compliant jitter cleaner with dual DSPLLs supporting SyncE ESMC processing and packet-based timing recovery. Use Value: Programmable loop bandwidth (20 Hz–4 kHz) and independent DSPLLs enable optimal filtering of both packet-delay variation and wander-achieving <0.01 ppm accuracy.	Use Scenario: Embedded clock generation inside QSFP-DD/OSFP pluggable transceivers for 100G–400G client interfaces. IC Role / Device Role / Timing Role: Compact, low-power clock multiplier converting a single 156.25 MHz reference into multiple SerDes lanes with matched skew. Use Value: 72-QFN 10×10 mm package and ±50 ps output skew support tight layout constraints while maintaining lane-to-lane phase alignment for PAM4 eye opening.

56G/112G/224G PAM4 SerDes Clocking

OTN Muxponders and Transponders

Use Scenario: High-speed optical interconnects requiring sub-100 fs jitter for 224G PAM4 signaling in AI/ML clusters and cloud infrastructure.

IC Role / Device Role / Timing Role: Jitter attenuator generating clean, low-phase-noise reference clocks for SerDes PHYs with deterministic latency via ZDM.

Use Value: Enables PCIe Gen6 and CEI-112G compliance with <55 fs RMS jitter and ≤35 ps hitless switch transient-reducing bit error rate in long-reach links.

Use Scenario: Aggregating multiple client-side OTN signals into line-side 400G/800G wavelengths in metro/core transport nodes.

IC Role / Device Role / Timing Role: Dual-DSPLL clock multiplier providing synchronized, jitter-cleaned clocks for OTN framers and FEC engines.

Use Value: Independent DSPLLA/B paths allow primary/backup reference sourcing with seamless failover-meeting ITU-T G.8262 ePRTC holdover stability requirements.

Synchronous Ethernet Line Cards

100G/200G/400G Optical Transceivers

Use Scenario: Timing distribution on high-density 400G line cards where EEC Option 1/2 compliance and phase alignment across 16+ ports are mandatory.

IC Role / Device Role / Timing Role: Stratum 3E-compliant jitter cleaner with dual DSPLLs supporting SyncE ESMC processing and packet-based timing recovery.

Use Value: Programmable loop bandwidth (20 Hz–4 kHz) and independent DSPLLs enable optimal filtering of both packet-delay variation and wander-achieving <0.01 ppm accuracy.

Use Scenario: Embedded clock generation inside QSFP-DD/OSFP pluggable transceivers for 100G–400G client interfaces.

IC Role / Device Role / Timing Role: Compact, low-power clock multiplier converting a single 156.25 MHz reference into multiple SerDes lanes with matched skew.

Use Value: 72-QFN 10×10 mm package and ±50 ps output skew support tight layout constraints while maintaining lane-to-lane phase alignment for PAM4 eye opening.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5362A-A15684-GMR	Same dual-DSPLL architecture but includes one MultiSynth block; supports fractional synthesis on all outputs vs. SI5362B's zero-MultiSynth design	Better suited for applications requiring arbitrary output frequencies beyond Q-divider limits (e.g., 322.265625 MHz for OTU4)	Select SI5362A if fractional output flexibility is required; SI5362B is preferred when integer-only synthesis suffices and lower complexity is desired
Si5363A-A15684-GMR	Three DSPLLs (DSPLLA/B/P) vs. SI5362B's two; higher integration for triple-reference redundancy but increased power (2.0 W vs. 2.9 W typical)	Targeted at ultra-high-availability systems like 5G massive MIMO baseband units requiring three independent sync sources	Choose SI5363A only when triple-DSPLL fault tolerance is mandated; SI5362B offers optimal cost/performance for dual-reference designs

Compared with Si5362A-A15684-GMR and Si5363A-A15684-GMR, the SI5362B-A15684-GMR delivers identical jitter performance and dual-DSPLL reliability at lower system complexity and reduced BOM count-making it ideal for cost-sensitive, dual-reference telecom and datacenter timing applications where fractional synthesis is not required.

Availability

SI5362B-A15684-GMR is available at Aetrix Electronics and suitable for 56G/112G SerDes clocking, OTN muxponder timing, and Synchronous Ethernet line cards requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5362B-A15684-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, timing, and precision analog solutions for communications, automotive, and industrial markets.

The Si536x family is engineered for ultra-low-jitter clock generation and jitter attenuation in high-speed digital infrastructure-targeting 112G/224G SerDes, coherent optics, and SyncE/PTP timing systems where phase noise and deterministic latency are critical.

FAQ

What is the maximum output frequency supported by the SI5362B-A15684-GMR?

The SI5362B-A15684-GMR supports up to 1.3 GHz using its integer Q-divider outputs. Fractional NA/NB divider outputs are limited to 650 MHz. This specification is confirmed in Table 10 of the official Skyworks datasheet (Rev. 206394C, Dec 2023) and aligns with the "B" grade designation in the ordering guide. The SI5362B-A15684-GMR does not support the 2.75 GHz range reserved for "H" grade variants like the Si5361H.

Does the SI5362B-A15684-GMR support hitless clock switching, and what is the typical phase transient?

Yes, the SI5362B-A15684-GMR supports enhanced hitless switching between synchronous inputs with a typical phase transient of 35 ps, as specified in Section 1 (Features) and Table 6 of the Skyworks datasheet. This capability applies when configured for phase buildout mode in ClockBuilder Pro and is critical for maintaining SerDes lock during reference failover in 100G+ systems.

How many DSPLLs and MultiSynths does the SI5362B-A15684-GMR contain?

The SI5362B-A15684-GMR contains two DSPLLs (DSPLLA and DSPLLB) and zero MultiSynth blocks, as explicitly stated in the Ordering Guide (Table 1) and Features list of the Skyworks datasheet. This distinguishes it from the Si5362A variant (two DSPLLs + one MultiSynth) and confirms its role as a dual-path, integer-only jitter attenuator.

What package type and footprint does the SI5362B-A15684-GMR use?

The SI5362B-A15684-GMR uses a 72-lead QFN package measuring 10 × 10 mm with 0.5 mm pitch and an exposed thermal pad, as documented in the Ordering Guide (Section 2) and Package Information (Page 4) of the Skyworks datasheet. This package is RoHS-compliant and optimized for thermal dissipation in high-density timing applications.

Can the SI5362B-A15684-GMR be programmed in-circuit, and what interfaces are supported?

Yes, the SI5362B-A15684-GMR supports in-circuit programming via I²C or SPI (3- or 4-wire), with on-chip non-volatile memory (NVM) enabling known-frequency power-up. Configuration is simplified using Skyworks' ClockBuilder Pro software, and factory programming is available for preconfigured frequency plans-as confirmed in Sections 1 and 2 of the official datasheet.

SI5362B-A15684-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: DSPLL™, MultiSynth™

Package/Case:: 72-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: -

Type:: Clock Multiplier, Jitter Attenuator

PLL:: Yes

Input:: LVCMOS, Crystal

Output:: CML, HCSL, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 4:18

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 1.3GHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 1.89V, 3.14V ~ 3.47V

Operating Temperature:: -40°C ~ 95°C (TA)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 72-QFN (10x10)

SI5362B-A15684-GMR FAQ

1.How can I place an order for SI5362B-A15684-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5362B-A15684-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5362B-A15684-GMR reliable?

The price and inventory of SI5362B-A15684-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5362B-A15684-GMR is usually 5 days.

3.What payment methods are accepted for SI5362B-A15684-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5362B-A15684-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5362B-A15684-GMR?

SI5362B-A15684-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5362B-A15684-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5362B-A15684-GMR?

For technical support, including SI5362B-A15684-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5362B-A15684-GMR requirements.

6.How does Aetrix verify that SI5362B-A15684-GMR is sourced from the original manufacturer or authorized distributors?

All SI5362B-A15684-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5362B-A15684-GMR meets industry standards.

7.What is the process for return or replacement of SI5362B-A15684-GMR?

All SI5362B-A15684-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5362B-A15684-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5362B-A15684-GMR part is unused and in its original packaging.

Return procedure for SI5362B-A15684-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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