Skyworks Solutions Inc. SI5364-F-BC

Overview

SI5364-F-BC from Silicon Laboratories is a SONET/SDH precision port card clock IC that phase-locks to one of three 19.44 MHz reference inputs and generates four independent ultra-low-jitter clock outputs at 19.44, 155.52, or 622.08 MHz. It implements DSPLL™ technology with no external loop filter components, supports Stratum 3/3E and SMC-compliant hitless switching, and delivers 0.26 psRMS (50 kHz–80 MHz) jitter generation. It is deployed in OC-192/OC-48 line cards requiring telecom-grade timing integrity.

For engineers reviewing the SI5364-F-BC datasheet, SI5364-F-BC pinout, SI5364-F-BC application, or SI5364-F-BC equivalent, key selection considerations include its 4-output synchronous clock synthesis capability, selectable 800–6400 Hz PLL bandwidth, FEC rate scaling (255/238 or 238/255), digital hold mode with ±7 ppm initial accuracy, and compliance with Telcordia GR-1244-CORE phase transient limits.

Technical Context

The SI5364-F-BC integrates a digitally controlled DSPLL with programmable loop bandwidth (800/1600/3200/6400 Hz via BWSEL[1:0]), enabling precise trade-offs between jitter attenuation and generation. Its input monitoring circuitry provides loss-of-signal (LOS) and frequency offset (FOS) alarms for each of three differential clock inputs (CLKIN_A, CLKIN_B, REF/CLKIN_F), supporting automatic revertive/non-revertive switching with sub-200 ps phase step magnitude.

Each of the four differential clock outputs (CLKOUT_1 to CLKOUT_4) is independently configured via FRQSEL_[1:0] pins for 1×, 8×, or 32× multiplication of the selected input clock, with optional FEC scaling applied globally via FEC[1:0]. The device includes an 8 kHz frame sync output (FSYNC), SYNCIN alignment input, and digital hold functionality activated on input loss, maintaining output frequency within ±30 ppm/°C drift.

Key Specifications

Pinout & Package

The SI5364-F-BC is housed in an 11 × 11 mm, 64-pin CBGA package with exposed thermal pad. Pin assignments follow the bottom-view layout defined in Silicon Labs Rev. 2.2 datasheet Section 3 and Figure 7.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar precision clock generation applications.

Compared with Si5362-F-BC, the SI5364-F-BC adds two clock outputs and FSYNC for full OC-192 port card coverage; compared with LMK04832ISQE/NOPB, it offers lower power, smaller footprint, and built-in telecom alarm logic but less flexible phase control.

Availability

SI5364-F-BC is available at Aetrix Electronics and suitable for SONET/SDH line cards, terabit routers, digital cross-connect systems, and core switches requiring stable component supply with full traceability and long-term lifecycle support.

Supply support for SI5364-F-BC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Laboratories is a fabless semiconductor company specializing in timing, wireless, and sensor solutions for communications, industrial, and consumer markets.

The SI5364-F-BC belongs to Silicon Labs' DSPLL™ precision clock IC product line, engineered specifically for telecom infrastructure applications requiring Stratum-grade timing, hitless switching, and FEC-aware clock synthesis.

FAQ

What is the primary function of the SI5364-F-BC in telecom systems?

The SI5364-F-BC serves as a precision clock generator and switch for SONET/SDH port cards, accepting up to three 19.44 MHz references and producing four independent, ultra-low-jitter outputs at 19.44/155.52/622.08 MHz. Its DSPLL™ architecture enables Stratum 3E-compliant timing with hitless switching, digital hold, and FEC scaling - all critical for OC-192/STM-64 line card reliability. The SI5364-F-BC replaces multi-chip timing solutions with a single, fully integrated IC.

Does the SI5364-F-BC require external loop filter components?

No, the SI5364-F-BC does not require external loop filter components. Its DSPLL™ technology replaces the analog loop filter with a digital signal processing algorithm that controls the VCO, eliminating sensitive analog nodes and reducing design complexity. This allows the SI5364-F-BC to achieve 0.26 psRMS jitter generation (50 kHz–80 MHz) while simplifying PCB layout and improving immunity to board-level noise - a key advantage over traditional analog PLLs.

How does the SI5364-F-BC support FEC rate compatibility?

The SI5364-F-BC supports FEC rate compatibility through its FEC[1:0] control inputs, which apply global 255/238 or 238/255 scaling to all active clock outputs. For example, a 622.08 MHz non-FEC output becomes 666.51 MHz (255/238 × 622.08) when FEC[1:0] = 01, or a 20.83 MHz FEC input yields 622.08 MHz when FEC[1:0] = 10. This ensures interoperability with forward-error-corrected transport layers without requiring external dividers or multipliers - a core capability of the SI5364-F-BC.

What is the significance of the BWSEL[1:0] pins on the SI5364-F-BC?

The BWSEL[1:0] pins on the SI5364-F-BC select one of four discrete PLL loop bandwidths: 800 Hz, 1600 Hz, 3200 Hz, or 6400 Hz. This setting directly governs jitter transfer attenuation, phase transient slope, and jitter generation trade-offs. A lower bandwidth (e.g., 800 Hz) strongly attenuates incoming jitter but increases generated jitter; a higher bandwidth (e.g., 6400 Hz) improves tracking but reduces filtering. Engineers configure BWSEL[1:0] to match system-level jitter budgets - a defining feature of the SI5364-F-BC's adaptability.

Can the SI5364-F-BC maintain timing during loss of all reference clocks?

Yes, the SI5364-F-BC enters digital hold mode upon loss of all valid clock inputs, sustaining output frequency with ±7 ppm initial accuracy (first 100 ms) and ±16.2 ppm/°C drift over temperature. Its internal calibration and DSPLL architecture ensure holdover stability meets Stratum 3E requirements for telecom infrastructure. This capability is integral to the SI5364-F-BC's role in mission-critical systems where uninterrupted timing is mandatory during reference failures.