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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5364-G-BC

Name: SI5364-G-BC
Brand: Skyworks Solutions Inc.
SKU: SI5364-G-BC
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5364-G-BC

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 99-BCBGA

Datasheet:: SI5364-G-BC.pdf

Description:: IC CLOCK GENERATOR 99CBGA

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5364-G-BC from Silicon Laboratories is a SONET/SDH precision port card clock IC that phase-locks to one of three 19.44 MHz reference inputs and generates four independent ultra-low-jitter clock outputs at 19.44, 155.52, or 622.08 MHz. It implements DSPLL™ technology with no external loop filter components and supports Stratum 3/3E and SMC-compliant hitless switching for OC-192/OC-48 line cards.

For engineers reviewing the SI5364-G-BC datasheet, SI5364-G-BC pinout, SI5364-G-BC application, or SI5364-G-BC equivalent, key selection criteria include jitter generation (as low as 0.26 psRMS over 50 kHz–80 MHz), digital hold capability, FEC rate scaling (255/238 or 238/255), programmable PLL bandwidth (800–6400 Hz), and integrated clock monitoring with LOS/FOS alarms.

Technical Context

The SI5364-G-BC employs Silicon Labs' DSPLL™ architecture-a fully digital phase-locked loop that replaces analog loop filters with DSP-based control, enabling precise jitter attenuation and stable VCO frequency synthesis across voltage, temperature, and process variations. Its core function is synchronous clock multiplication (1×, 8×, or 32×) with optional FEC scaling, delivering deterministic phase alignment between outputs.

It integrates real-time input monitoring (LOS, FOS), automatic/manual revertive/non-revertive switching, and 8 kHz frame sync output. The device supports differential LVDS-compatible outputs (816–1100 mVPP), operates from a single 3.3 V supply, and features on-chip biasing for ac-coupled inputs-enabling robust operation in telecom timing applications without external passive tuning elements.

Key Specifications

Parameter	Value and Actual Design Meaning
Output jitter (RMS)	0.26 ps over 50 kHz–80 MHz bandwidth - meets OC-192/OC-48 Stratum 3E phase noise requirements
Input frequency range	18.14–22.60 MHz with FEC scaling - supports 19.44 MHz SONET references and forward/reverse FEC variants
Output frequencies	19.44 / 155.52 / 622.08 MHz (1×/8×/32×) - directly matches SONET OC-3/OC-12/OC-48 line rates
PLL bandwidth options	800 / 1600 / 3200 / 6400 Hz - selectable via BWSEL[1:0] pins to balance jitter attenuation vs. transient response
Digital hold accuracy	±7.0 ppm initial, ±16.2 ppm/°C drift - maintains timing integrity during reference loss in redundant systems
Supply voltage	3.135–3.465 V - compatible with standard 3.3 V rail; no level-shifting required
Operating temperature	–20 °C to +85 °C - qualified for commercial/industrial telecom equipment environments

Pinout & Package

The SI5364-G-BC is housed in an 11×11 mm CBGA package with 121 balls (0.8 mm pitch). Pin assignment follows the bottom-view layout specified in Rev. 2.5 datasheet Figure 5 and Table 3 (pages 22–23), supporting differential clock I/O, LVTTL control signals, and dedicated monitoring outputs.

Pin/Terminal	Circuit Role	Design Meaning
CLKIN_A+/–, CLKIN_B+/–, REF/CLKIN_F+/–	Differential clock inputs	Three independent 19.44 MHz reference paths with internal 1.5 V biasing; support ac-coupled single-ended drive
CLKOUT_1+ to CLKOUT_4–	Differential clock outputs	Four LVDS-compatible outputs (100 Ω load); each independently configurable for 19/155/622 MHz
FRQSEL_[1:0] ×4	Output frequency select	Per-output 2-bit control for 1×/8×/32× multiplication; enables mixed-rate clock distribution
FEC[1:0]	FEC scaling control	Selects 1/1, 255/238, or 238/255 scaling - essential for interoperability with FEC-enabled SONET gear
BWSEL[1:0]	PLL bandwidth select	Sets loop filter bandwidth (800–6400 Hz) to optimize jitter transfer vs. phase transient behavior
LOS_A/B/F, FOS_A/B	Alarm status outputs	Open-drain LVTTL flags indicating loss-of-signal or frequency offset beyond Stratum 3E thresholds
AUTOSEL, RVRT, MANCNTRL[1:0]	Switching control	Enables automatic revertive/non-revertive clock switchover or manual override with hitless transition

Key Features

Feature	Design Value
DSPLL™ architecture	Fully digital PLL eliminates external loop filter components, reducing BOM count and board area while ensuring consistent performance across temperature and voltage
Hitless clock switching	Phase-transient-limited switching (<200 ps step, <800 ps MTIE max) meets Telcordia GR-1244-CORE Stratum 3E requirements
Integrated FEC scaling	On-the-fly 255/238 or 238/255 clock rate adjustment enables seamless interoperation with FEC-encoded SONET/SDH infrastructure
Digital hold mode	Maintains output frequency within ±7 ppm for ≥100 ms after reference loss - critical for maintaining synchronization during failover
8 kHz frame sync output	FSYNC signal aligned to output clocks provides deterministic timing reference for framing logic in line cards

Applications

SONET/SDH Line Cards	Terabit Core Routers
Use Scenario: Generating synchronized 19.44 MHz, 155.52 MHz, and 622.08 MHz clocks from redundant 19.44 MHz references on OC-192/OC-48 port cards. IC Role / Device Role / Timing Role: Precision clock generator and switch with Stratum 3E compliance, providing jitter-clean outputs for SERDES and framer ICs. Use Value: Enables hitless switchover between primary/backup references while maintaining <200 ps phase step - avoids packet loss during clock rearrangement.	Use Scenario: Distributing low-jitter timing across multiple switching ASICs and PHY layers in high-density router line cards. IC Role / Device Role / Timing Role: Centralized clock source with four independent outputs, each configurable for different data rates (e.g., 155.52 MHz for control plane, 622.08 MHz for data plane). Use Value: Eliminates need for discrete clock buffers and external loop filters, reducing layout complexity and improving system-level jitter margin by >3 dB.
Digital Cross-Connect Systems	Core Switch Fabric Timing
Use Scenario: Providing phase-aligned clocks to multiple TDM switching matrices and add-drop multiplexers in legacy SDH networks. IC Role / Device Role / Timing Role: Stratum 3/3E-compliant clock distributor with digital hold and FEC scaling for backward compatibility with older FEC-equipped nodes. Use Value: Supports both non-FEC (19.44 MHz) and FEC-scaled (20.83 MHz) inputs, enabling gradual network upgrades without timing infrastructure replacement.	Use Scenario: Synchronizing distributed switch fabric clocks across multi-board chassis with tight skew tolerance. IC Role / Device Role / Timing Role: Low-skew clock generator with <400 ps inter-output phase skew - ensures deterministic latency across parallel data paths. Use Value: Reduces timing uncertainty in cut-through switching, improving worst-case latency predictability by up to 1.2 ns per hop.

SONET/SDH Line Cards

Terabit Core Routers

Use Scenario: Generating synchronized 19.44 MHz, 155.52 MHz, and 622.08 MHz clocks from redundant 19.44 MHz references on OC-192/OC-48 port cards.

IC Role / Device Role / Timing Role: Precision clock generator and switch with Stratum 3E compliance, providing jitter-clean outputs for SERDES and framer ICs.

Use Value: Enables hitless switchover between primary/backup references while maintaining <200 ps phase step - avoids packet loss during clock rearrangement.

Use Scenario: Distributing low-jitter timing across multiple switching ASICs and PHY layers in high-density router line cards.

IC Role / Device Role / Timing Role: Centralized clock source with four independent outputs, each configurable for different data rates (e.g., 155.52 MHz for control plane, 622.08 MHz for data plane).

Use Value: Eliminates need for discrete clock buffers and external loop filters, reducing layout complexity and improving system-level jitter margin by >3 dB.

Digital Cross-Connect Systems

Core Switch Fabric Timing

Use Scenario: Providing phase-aligned clocks to multiple TDM switching matrices and add-drop multiplexers in legacy SDH networks.

IC Role / Device Role / Timing Role: Stratum 3/3E-compliant clock distributor with digital hold and FEC scaling for backward compatibility with older FEC-equipped nodes.

Use Value: Supports both non-FEC (19.44 MHz) and FEC-scaled (20.83 MHz) inputs, enabling gradual network upgrades without timing infrastructure replacement.

Use Scenario: Synchronizing distributed switch fabric clocks across multi-board chassis with tight skew tolerance.

IC Role / Device Role / Timing Role: Low-skew clock generator with <400 ps inter-output phase skew - ensures deterministic latency across parallel data paths.

Use Value: Reduces timing uncertainty in cut-through switching, improving worst-case latency predictability by up to 1.2 ns per hop.

Equivalent & Alternatives

The following parts are listed as comparable options for similar precision clock generation applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5362-G-GM	2-output variant; identical DSPLL core, same jitter specs, but lacks two CLKOUT channels and FEC[1:0] control	Suitable only for simpler port cards requiring ≤2 clocks; cannot support full OC-192 quad-clock architecture	Select when BOM cost reduction is prioritized over flexibility and future-proofing for multi-rate expansion
LMK04828BISQE/NOPB	Two-stage jitter cleaner with dual-loop architecture; higher power (320 mA), larger 7×7 mm QFN, requires external VCXO	Better suited for ultra-low-jitter clean-up of noisy sources rather than native SONET reference synthesis	Choose when input reference quality is poor and sub-0.15 psRMS jitter is mandatory - not a drop-in replacement for SI5364-G-BC

Compared with Si5362-G-GM, SI5364-G-BC delivers full quad-output capability and FEC scaling essential for OC-192 line cards; versus LMK04828BISQE/NOPB, it offers lower power, smaller footprint, and integrated reference synthesis - making it optimal for space-constrained, high-channel-count telecom timing.

Availability

SI5364-G-BC is available at Aetrix Electronics and suitable for SONET/SDH line cards, terabit routers, and digital cross-connect systems requiring stable component supply, long-term lifecycle support, and guaranteed traceability for telecom infrastructure deployments.

Supply support for SI5364-G-BC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Laboratories is a fabless semiconductor company specializing in timing, wireless, and MCU solutions for communications, industrial, and consumer markets.

The SI5364-G-BC belongs to Silicon Labs' precision clock IC product line, engineered specifically for carrier-grade SONET/SDH port card timing with Stratum 3E compliance, FEC interoperability, and ultra-low jitter generation.

FAQ

What is the minimum input clock frequency supported by the SI5364-G-BC with FEC scaling?

The SI5364-G-BC supports a minimum input frequency of 18.140 MHz when FEC[1:0] = 01 (255/238 scaling), enabling compatibility with FEC-encoded 19.44 MHz references. This is verified in Table 3 (page 8) of the Rev. 2.5 datasheet under "Input Clock Frequency (forward FEC)". The device maintains full functionality-including jitter performance and switching-across this extended range.

Does the SI5364-G-BC require external loop filter components?

No, the SI5364-G-BC does not require external loop filter components. Its DSPLL™ architecture uses a digital signal processing algorithm to replace the analog loop filter, eliminating capacitors and resistors traditionally needed for stability and bandwidth control. This is confirmed in the Features section (page 1) and Functional Description (page 15), where Silicon Labs explicitly states "no external components (other than a resistor and standard bypassing)".

How does the SI5364-G-BC handle clock loss during automatic switching?

Upon loss of all valid inputs, the SI5364-G-BC enters digital hold mode with initial frequency accuracy of ±7.0 ppm and drift of ±16.2 ppm/°C. It maintains output until a valid reference is restored, with recovery time of 0.09–14.1 s depending on VALTIME setting. This behavior is documented in Table 4 (page 11) under "Initial Frequency Accuracy in Digital Hold Mode" and "Recovery Time for Clearing an LOS or FOS Condition".

Can the SI5364-G-BC generate 622.08 MHz output from a 20.83 MHz FEC input?

Yes, the SI5364-G-BC can generate 622.08 MHz from a 20.83 MHz FEC input by configuring FRQSEL_[1:0] = 11 (32×) and FEC[1:0] = 10 (238/255 scaling). This is explicitly described in Section 2.1.1 (page 16) and Table 9 (page 16), where the example shows "622.08 MHz output … generated from a 20.83 MHz input clock (a FEC rate)" using 238/255 scaling.

What is the maximum allowable phase transient slope during clock switching for the SI5364-G-BC?

The maximum phase transient slope for the SI5364-G-BC is 36 ps/μs under auto-switching with BWSEL[1:0] = 11 (6400 Hz bandwidth), as specified in Table 4 (page 12) under "Clock Output Phase Step Slope3-Auto Switching". This value is well below Telcordia GR-1244-CORE limits for Stratum 3E clocks and ensures compliant MTIE behavior during rearrangement.

SI5364-G-BC Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: DSPLL®

Package/Case:: 99-BCBGA

Packaging:: Tray

Product Status:: Obsolete

Programmable:: Not Verified

Type:: Clock Generator

PLL:: Yes

Input:: Clock

Output:: CML

Number of Circuits:: 1

Ratio - Input:Output:: 3:4

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 675MHz

Divider/Multiplier:: No/Yes

Voltage - Supply:: 3.135V ~ 3.465V

Operating Temperature:: -20°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 99-CBGA (11x11)

SI5364-G-BC FAQ

1.How can I place an order for SI5364-G-BC through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5364-G-BC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5364-G-BC reliable?

The price and inventory of SI5364-G-BC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5364-G-BC is usually 5 days.

3.What payment methods are accepted for SI5364-G-BC?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5364-G-BC transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5364-G-BC?

SI5364-G-BC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5364-G-BC order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5364-G-BC?

For technical support, including SI5364-G-BC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5364-G-BC requirements.

6.How does Aetrix verify that SI5364-G-BC is sourced from the original manufacturer or authorized distributors?

All SI5364-G-BC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5364-G-BC meets industry standards.

7.What is the process for return or replacement of SI5364-G-BC?

All SI5364-G-BC units undergo pre-shipment inspection (PSI). If there is an issue with SI5364-G-BC, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5364-G-BC part is unused and in its original packaging.

Return procedure for SI5364-G-BC:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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