Skyworks Solutions Inc. SI5367C-C-GQR

Overview

SI5367C-C-GQR from Silicon Laboratories is a µP-programmable precision clock multiplier IC implementing 3rd-generation DSPLL® technology. It accepts four differential clock inputs (10–710 MHz), generates five programmable-frequency outputs (2 kHz–945 MHz, up to 1.4 GHz at select ratios), delivers jitter as low as 0.6 ps rms (50 kHz–80 MHz), and supports LVPECL/LVDS/CML/CMOS output formats - used in SONET/SDH line cards and high-speed data converter clocking.

For engineers reviewing the SI5367C-C-GQR datasheet, SI5367C-C-GQR pinout, SI5367C-C-GQR application, or SI5367C-C-GQR equivalent, key selection considerations include its digitally programmable loop bandwidth (150 kHz–1.3 MHz), integrated loop filter, ITU G.709 FEC ratio support (255/238, 255/237, 255/236), LOS alarm outputs, and 100-pin TQFP package with I²C/SPI configuration interface.

Technical Context

The SI5367C-C-GQR uses a single DSPLL core with independent N-divider paths for each of its five outputs, enabling simultaneous synthesis of disparate frequencies from a common reference without jitter attenuation. Its input clock selection supports manual or automatic switching across four inputs, with loss-of-signal detection and freeze-on-fail behavior to maintain DCO frequency stability during input failure.

Programmability includes per-output signal format (LVPECL, LVDS, CML, CMOS), phase offset adjustment (800 ps–2.2 ns resolution), and bypass mode that routes input clocks directly to outputs-bypassing the PLL-for system-level debugging. The on-chip voltage regulator supports 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10% operation.

Key Specifications

Pinout & Package

SI5367C-C-GQR is housed in a 14 × 14 mm, 100-pin TQFP package with exposed thermal pad. Pin functions are defined per the official Si5367 datasheet Rev. 1.0, Section 6 ("Pin Descriptions").

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock multiplier applications.

Compared with SI5367C-C-GQR, the Si5332A-D-GM offers superior jitter and frequency range but requires package and power redesign, while the Si5341-A02819-GM provides identical timing performance in a functionally equivalent 4-output variant with mechanical compatibility.

Availability

SI5367C-C-GQR is available at Aetrix Electronics and suitable for SONET/SDH line cards, 10GbE switching platforms, and wireless base station timing applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5367C-C-GQR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Laboratories is a fabless semiconductor company specializing in timing, wireless, and sensor technologies for communications, industrial, and consumer markets.

The Si5367 product line was designed for high-performance, µP-programmable clock multiplication in telecom and networking infrastructure - emphasizing jitter-critical applications where external VCXOs and loop filters must be eliminated.

FAQ

What is the maximum output frequency supported by the SI5367C-C-GQR?

The SI5367C-C-GQR supports up to 945 MHz across its full operating range. At select integer-N ratios (N1 = 4), it achieves frequencies up to 1.4 GHz - verified in Table 3 of the datasheet under "Output Frequency" with CKOF parameter. This capability is used in OC-192 and 10GFC applications requiring 1.2288 GHz or 1.25 GHz clocks.

Does the SI5367C-C-GQR support I²C and SPI interfaces simultaneously?

No. The SI5367C-C-GQR supports either I²C or SPI control, selected via the CMODE pin (low = I²C, high = SPI). Both interfaces share the same functional register map and configuration capabilities, but only one can be active at a time - confirmed in Figures 4 and 5 of the datasheet.

What output signal formats does the SI5367C-C-GQR support, and are they configurable per output?

The SI5367C-C-GQR supports LVPECL, LVDS, CML, and CMOS output formats, and each of its five outputs can be independently configured via SFOUTx_REG registers (Registers 5–7). Format selection is validated in Table 2 and Section 3.1 of the datasheet, with current and voltage specifications provided per format.

How does the SI5367C-C-GQR handle loss-of-signal (LOS) conditions on its input clocks?

The SI5367C-C-GQR monitors all four CKIN inputs for LOS and asserts dedicated LOSn alarm outputs. When triggered, it freezes the DCO frequency near its last valid value to maintain output stability. The LOS trigger window is programmable and scales with input period (LOSTRIG = 4.5 × N3 × TCKIN), as specified in Table 3.

Is the SI5367C-C-GQR pin-compatible with other devices in the Si53xx family?

No. The SI5367C-C-GQR uses a unique 100-pin TQFP footprint not shared with other Si53xx devices. While register maps and DSPLL® architecture are consistent across the family, physical pinout differs - confirmed by comparing Package Outline drawings in datasheets for Si5332, Si5341, and Si5367.