Skyworks Solutions Inc. SI5368A-C-GQ

Overview

SI5368A-C-GQ from Skyworks Solutions is a jitter-attenuating precision clock multiplier IC implementing third-generation DSPLL® technology. It accepts four differential or single-ended clock inputs (2 kHz–710 MHz), generates five programmable outputs (2 kHz–945 MHz, up to 1.4 GHz in select modes), and delivers ultra-low jitter of 300 fs rms (12 kHz–20 MHz). It operates from 1.8/2.5/3.3 V and supports LVPECL, LVDS, CML, and CMOS output formats for high-performance timing in telecom line cards and data converter clocking.

For engineers reviewing the SI5368A-C-GQ datasheet, SI5368A-C-GQ pinout, SI5368A-C-GQ application, or SI5368A-C-GQ equivalent, key selection criteria include its sub-1 ps rms jitter performance, hitless input switching with phase build-out, digitally programmable loop bandwidth (60 Hz–8.4 kHz), GR-253-CORE compliance, and support for ITU G.709 and custom FEC ratios.

Technical Context

The SI5368A-C-GQ integrates a fully digital DSPLL® core with independent N-divider paths for all four inputs and five outputs, enabling arbitrary frequency synthesis without external VCXO or analog loop filters. Its PLL loop bandwidth is digitally configurable to optimize jitter attenuation for specific reference and payload frequencies.

It implements SONET frame sync switching and regeneration, supports holdover and freerun modes, and provides LOL/LOS/FOS alarm outputs plus digitally controlled output phase adjustment. Input clock selection includes manual or automatic hitless switching with phase alignment across inputs.

Key Specifications

Pinout & Package

SI5368A-C-GQ is housed in a 14 × 14 mm, 100-pin TQFP package with exposed thermal pad. Pin assignments are validated per Skyworks Si5368 datasheet Rev. 1.0 (March 2022), pages 79–85.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter-attenuating clock multiplier applications.

Compared with SI5368A-C-GQ, Si5365B-A-GM offers identical jitter performance but omits frame sync capability, while LTC6955IUF#PBF delivers lower integration and higher jitter-making SI5368A-C-GQ optimal for SONET/OTN and multi-standard telecom timing where jitter, flexibility, and standards compliance are critical.

Availability

SI5368A-C-GQ is available at Aetrix Electronics and suitable for SONET/SDH line cards, 10GbE switching infrastructure, and high-speed data converter clocking requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5368A-C-GQ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5368 product line was designed specifically for carrier-grade timing applications requiring sub-1 ps jitter, GR-253-CORE compliance, and multi-protocol synchronization-including SONET/SDH, OTN, SyncE, and ITU G.709 transport layers.

FAQ

What is the maximum output frequency supported by SI5368A-C-GQ in LVPECL format?

The SI5368A-C-GQ supports up to 945 MHz in LVPECL format when the output divider N1 ≥6. At N1 = 5, it reaches 970–1134 MHz; at N1 = 4, it achieves 1.213–1.4 GHz-but only in non-CMOS formats. LVPECL operation requires VDD ≥2.5 V and proper termination per datasheet guidelines. SI5368A-C-GQ maintains jitter performance within specification across this full range when configured per Skyworks DSPLLsim recommendations.

Does SI5368A-C-GQ support automatic hitless switching between its four clock inputs?

Yes, SI5368A-C-GQ supports both manual and automatically controlled hitless switching across all four clock inputs (CKIN1–CKIN4), including phase build-out to align output phase during transitions. This functionality is implemented in hardware and does not require host processor intervention. SI5368A-C-GQ maintains continuous output clocking with zero cycle slips or phase jumps, making it suitable for carrier-class redundancy schemes in SONET/SDH and OTN systems.

Can SI5368A-C-GQ generate frame sync signals compliant with SONET/SDH standards?

Yes, SI5368A-C-GQ can configure its fifth output (FS_OUT+ / FS_OUT–) as a 2–512 kHz differential frame sync signal, phase-aligned to any selected high-speed output clock. It supports SONET frame sync switching and regeneration, meeting ITU-T G.783 and GR-253-CORE requirements. SI5368A-C-GQ also supports custom FEC ratios (e.g., 253/226, 239/237) for precise timing alignment in forward error correction transport layers.

What power supply voltages are supported by SI5368A-C-GQ, and how do they affect output format selection?

SI5368A-C-GQ operates from a single 1.8 V, 2.5 V, or 3.3 V supply. LVPECL outputs require VDD ≥2.5 V; CMOS outputs are limited to ≤212.5 MHz and draw higher current. Power constraints apply: with four enabled LVPECL or CMOS outputs, the fifth must be disabled; with five enabled outputs, no more than three may be LVPECL or CMOS. SI5368A-C-GQ's supply voltage directly determines compatible output formats and maximum enabled output count per datasheet Table 1 and Note 6.

How is jitter performance specified for SI5368A-C-GQ, and which integration bands are guaranteed?

SI5368A-C-GQ specifies jitter as 300 fs rms (12 kHz–20 MHz), 274 fs rms (20 kHz–80 MHz), and 166 fs rms (4 MHz–80 MHz), all measured per GR-253-CORE methodology with –20 dB/dec low-pass and –60 dB/dec high-pass filtering. It meets OC-192 GR-253-CORE jitter limits (≤1.0 ps rms) with margin. SI5368A-C-GQ's jitter generation is guaranteed across temperature (–40°C to +85°C) and supply (1.8/2.5/3.3 V) ranges per Table 5 and Figure 3 in the official datasheet.