Skyworks Solutions Inc. SI5368A-C-GQR

Overview

SI5368A-C-GQR from Skyworks Solutions is a jitter-attenuating precision clock multiplier IC with DSPLL® technology, accepting four 2 kHz–710 MHz inputs and generating five 2 kHz–945 MHz outputs (up to 1.4 GHz in select modes). It delivers ultra-low jitter of 300 fs rms (12 kHz–20 MHz), supports I²C/SPI programming, and operates from 1.8/2.5/3.3 V supply. It is deployed in SONET/SDH line cards and high-speed data converter clocking.

For engineers reviewing the SI5368A-C-GQR datasheet, SI5368A-C-GQR pinout, SI5368A-C-GQR application, or SI5368A-C-GQR equivalent, key selection criteria include sub-1 ps RMS jitter compliance with GR-253-CORE, programmable loop bandwidth (60 Hz–8.4 kHz), five configurable output formats (LVPECL/LVDS/CML/CMOS), hitless input switching, and frame-sync regeneration for OTN/WDM systems.

Technical Context

The SI5368A-C-GQR implements Skyworks' third-generation DSPLL® architecture with a digitally programmable loop bandwidth (60 Hz–8.4 kHz), enabling application-level jitter optimization without external VCXO or analog loop filter components. Its core PLL synthesizes outputs from a common high-frequency VCO, with independent N-divider chains per output (N1–N5) and input clock selection logic supporting manual or automatic hitless switching.

It integrates SONET frame sync switching and regeneration, ITU G.709 FEC ratio support (e.g., 255/238), and alarm outputs (LOL/LOS/FOS). The device supports holdover and freerun modes, digital phase adjustment per output, and dual-reference operation via crystal (XA/XB) or external clock inputs.

Key Specifications

Pinout & Package

The SI5368A-C-GQR is housed in a 14 × 14 mm, 100-pin thin quad flat package (TQFP) with exposed thermal pad. Pin assignments are validated per Skyworks Si5368 datasheet Rev. 1.0 (March 2022), pages 79–85.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter-attenuating clock multiplier applications.

Compared with SI5368A-C-GQR, Si5365B-A-GM offers identical jitter performance and footprint but lacks the fifth output and 1.4 GHz capability, while LMK04832ISQE/NOPB adds JESD204B features at higher power and complexity-making SI5368A-C-GQR optimal for multi-standard telecom clock trees needing maximum flexibility and minimal external components.

Availability

SI5368A-C-GQR is available at Aetrix Electronics and suitable for SONET/SDH line cards, OTN/WDM muxponders, and high-speed data converter clocking requiring stable component supply, long-term lifecycle assurance, and full traceability.

Supply support for SI5368A-C-GQR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5368 family is designed for high-performance timing in telecom and networking equipment, delivering jitter-attenuating clock multiplication with integrated DSPLL® technology to replace discrete PLL + VCXO + loop filter subsystems.

FAQ

What is the minimum input frequency supported by the SI5368A-C-GQR?

The SI5368A-C-GQR supports input frequencies as low as 2 kHz on all four clock inputs (CKIN1–CKIN4), enabling compatibility with low-frequency reference sources such as GPS-disciplined oscillators or atomic clock outputs. This capability is confirmed in Table 3 of the Skyworks Si5368 datasheet Rev. 1.0, which specifies CKNF = 0.002 MHz minimum. The SI5368A-C-GQR maintains full DSPLL functionality-including jitter attenuation and programmable multiplication-even at these ultra-low input rates.

Does the SI5368A-C-GQR support SONET frame sync regeneration?

Yes, the SI5368A-C-GQR supports SONET/SDH frame sync regeneration via dedicated FS_OUT+ and FS_OUT– pins. It can generate a 2–512 kHz frame sync signal phase-aligned to any of its high-speed outputs, with built-in support for OC-48 and OC-192 frame structures. The SI5368A-C-GQR also supports ITU G.709 and custom FEC ratios including 255/238 and 253/226, as documented in the Features section and functional description of the datasheet.

What output signal formats does the SI5368A-C-GQR support?

The SI5368A-C-GQR supports LVPECL, LVDS, CML, and CMOS output formats across all five clock outputs. Format selection is per-output and programmable via register settings. LVPECL requires VDD ≥2.5 V; CMOS outputs are limited to ≤212.5 MHz. These capabilities are specified in the Features list and Table 2 (DC Characteristics) of the Skyworks Si5368 datasheet Rev. 1.0, confirming direct interface to FPGAs, ASICs, and SerDes without external level translation.

How is the loop bandwidth configured on the SI5368A-C-GQR?

The SI5368A-C-GQR features a digitally programmable DSPLL® loop bandwidth ranging from 60 Hz to 8.4 kHz, set via I²C or SPI register writes. This allows real-time optimization of jitter attenuation versus transient response for specific application requirements-such as minimizing wander in synchronous Ethernet or suppressing phase noise in RF sampling systems. The loop bandwidth configuration is detailed in Section 4.2 and Register Map sections of the Si5368 datasheet Rev. 1.0.

What is the RMS jitter performance of the SI5368A-C-GQR at 622.08 MHz?

At 622.08 MHz output with LVPECL format and 120 Hz loop bandwidth, the SI5368A-C-GQR achieves 300 fs rms jitter (12 kHz–20 MHz integration band), as stated in the Features section and verified in Table 5 (Jitter Generation) and Table 8 (RMS Jitter by Band) of the Skyworks Si5368 datasheet Rev. 1.0. This performance meets GR-253-CORE OC-192 specifications and is measured under worst-case conditions (TA = 85 °C, VDD = 2.5 V).