Skyworks Solutions Inc. SI5374B-A-BL

Overview

SI5374B-A-BL from Skyworks Solutions is a 4-PLL, jitter-attenuating precision clock multiplier IC designed for high-port-count optical line cards requiring independent timing domains. It accepts dual inputs per PLL (2 kHz–710 MHz), generates two synchronous outputs per PLL (2 kHz–808 MHz), delivers 350 fs rms (12 kHz–20 MHz) jitter, supports LVPECL/LVDS/CML/CMOS output formats, and operates from single 1.8 V or 2.5 V supply.

For engineers reviewing the SI5374B-A-BL datasheet, SI5374B-A-BL pinout, SI5374B-A-BL application, or SI5374B-A-BL equivalent, key selection criteria include sub-1 ps jitter performance, programmable DSPLL loop bandwidth (4–525 Hz), ITU-T G.8251 compliance, hitless input switching, and support for custom FEC ratios (e.g., 239/237, 255/238).

Technical Context

The SI5374B-A-BL integrates four independent DSPLL® engines, each with fully programmable N/M synthesis, digitally adjustable loop bandwidth, and integrated loop filter-eliminating external VCXO and passive loop components. Each DSPLL accepts two differential inputs and generates two differential outputs with configurable signal format and phase offset.

It implements automatic/manual hitless clock switching, loss-of-signal (LOS) and loss-of-lock (LOL) monitoring, holdover operation using internal oscillator routing, and I²C-based configuration (SCL/SDA). The device supports simultaneous free-run and synchronous modes, with reference oscillator input (OSC_P/N) enabling ultra-low-jitter generation without crystal dependency.

Key Specifications

Pinout & Package

SI5374B-A-BL is housed in a 10 mm × 10 mm, 80-pin PBGA package with 0.5 mm pitch and lead-free finish. Pin functions are defined per DSPLL domain (A/B/C/D), with dedicated input, output, control, and power terminals.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter-attenuating clock multiplier applications.

Compared with Si5375B-A-BL and LMK04832RHAT, the SI5374B-A-BL delivers optimal balance of 4-domain isolation, ITU-T compliance, and 8-output flexibility for optical transport line cards-without over-specifying holdover or adding unnecessary JESD204B features.

Availability

SI5374B-A-BL is available at Aetrix Electronics and suitable for 100G optical line cards, carrier Ethernet switches, and OTN muxponders requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5374B-A-BL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, timing, and precision analog solutions for infrastructure, automotive, and mobile markets.

The SI5374B-A-BL belongs to Skyworks' DSPLL® precision clock family, engineered specifically for telecom transport equipment requiring sub-1 ps jitter, multi-domain timing isolation, and ITU-T-compliant jitter attenuation in high-port-count line cards.

FAQ

What is the maximum output frequency supported by the SI5374B-A-BL in CMOS format?

The SI5374B-A-BL supports a maximum output frequency of 212.5 MHz in CMOS format. This limit is defined by the device's internal driver strength and load capacitance constraints (5 pF), as specified in Table 3 of the datasheet. Higher frequencies require LVPECL, LVDS, or CML output configurations, which support up to 808 MHz. For 10G FC or OTU4 applications, non-CMOS formats must be used.

Does the SI5374B-A-BL require an external crystal or can it operate with only a clock input?

The SI5374B-A-BL requires an external low-jitter oscillator (not a crystal) connected to OSC_P/OSC_N pins for ultra-low-jitter operation and holdover functionality. A crystal cannot be substituted-only a differential or single-ended XO (109–125.5 MHz) is supported. However, the device can accept reference clocks directly on CKIN pins for synchronous operation without OSC, though holdover and lowest-jitter performance depend on OSC_P/N.

How many independent timing domains does the SI5374B-A-BL support?

The SI5374B-A-BL supports four fully independent timing domains via its four DSPLL engines (A, B, C, D). Each domain has dedicated inputs, outputs, loop filters, and configuration registers-enabling simultaneous generation of unrelated frequencies (e.g., 107.09 GHz for OTU4, 622.08 MHz for SONET, 155.52 MHz for STM-1, and 19.44 MHz for OTU1) with zero inter-domain jitter coupling.

What is the purpose of the RSTL_A–RSTL_D pins on the SI5374B-A-BL?

The RSTL_A–RSTL_D pins are asynchronous active-low reset inputs for each DSPLL domain. Asserting RSTL_x resets the corresponding DSPLL's VCO, dividers, and state machines. Skyworks recommends tying all four RSTL pins together externally (not under the BGA) to ensure synchronized initialization across domains-preventing VCO drift-induced crosstalk during power-up or reconfiguration of the SI5374B-A-BL.

Which industry standards does the SI5374B-A-BL meet for jitter performance?

The SI5374B-A-BL meets ITU-T G.8251 (for OTN applications) and Telcordia GR-253-CORE OC-192 jitter specifications. Its typical 350 fs rms (12 kHz–20 MHz) and 410 fs rms (50 kHz–80 MHz) jitter values are measured per DSPLL output under standard conditions (622.08 MHz, LVPECL, 100 Ω load) and validated across temperature and supply voltage ranges per Table 5 of the datasheet.