Skyworks Solutions Inc. SI5380A-B08455-GM

Overview

SI5380A-B08455-GM from Skyworks Solutions is a 12-output, integer-based JESD204B jitter attenuator and clock multiplexer optimized for wireless infrastructure. It delivers ultra-low phase noise (–159 dBc/Hz floor), 65 fs RMS jitter (12 kHz–20 MHz), and supports DCLK/SYSREF generation with hitless switching across four differential or LVCMOS inputs. Used in remote radio units and LTE-A base stations requiring precise timing synchronization.

For engineers reviewing the SI5380A-B08455-GM datasheet, SI5380A-B08455-GM pinout, SI5380A-B08455-GM application, or SI5380A-B08455-GM equivalent, key selection considerations include DSPLL loop bandwidth configurability (0.1 Hz–100 Hz), holdover frequency averaging over 120 s of history, JESD204B Subclass 0/1 compliance, and factory pre-programmed configuration via ClockBuilder Pro.

Technical Context

The SI5380A-B08455-GM implements Skyworks' 4th-generation DSPLL™ architecture with a 15 GHz VCO, programmable digital loop filter, and integrated 54 MHz crystal oscillator. It synthesizes up to 10 integer-related output frequencies from any of four input clocks or freerun mode, eliminating external VCXO and analog loop filter components.

Its functional block includes independent R-divider paths per output, configurable crosspoint mux, status monitoring (LOS/OOF/LOL), and dual-mode serial interface (I²C/SPI) with on-chip OTP NVM. The device supports ramped holdover exit, fastlock acquisition (100 Hz–4 kHz), and zero-delay mode when IN3 is configured as FB_IN.

Key Specifications

Pinout & Package

The SI5380A-B08455-GM is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5380 Rev D datasheet Section 9 (Pin Description).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Compared with SI5380A-B08455-GM, Si5386A-D-GM offers enhanced JESD204B phase control but lacks pin compatibility, while LTC6957-3IUF#PBF achieves lower jitter at the cost of system-level integration, holdover resilience, and multi-output scalability.

Availability

SI5380A-B08455-GM is available at Aetrix Electronics and suitable for wireless infrastructure, remote radio units, and JESD204B data converter systems requiring stable component supply throughout product lifecycles.

Supply support for SI5380A-B08455-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, automotive, and industrial markets.

The SI5380A-B08455-GM belongs to Skyworks' high-performance clock generation portfolio, designed specifically for ultra-low-jitter, multi-output timing in wireless infrastructure equipment demanding JESD204B compliance and robust holdover operation.

FAQ

What is the primary function of the SI5380A-B08455-GM in wireless base station designs?

The SI5380A-B08455-GM serves as a jitter-attenuating clock multiplexer that generates up to 12 synchronized, ultra-low-jitter outputs for RF transceivers, FPGAs, and data converters in 4G/LTE and small cell base stations. Its DSPLL architecture eliminates external VCXOs and analog filters while maintaining phase coherence across DCLK and SYSREF signals required by JESD204B.

Does the SI5380A-B08455-GM support JESD204B Subclass 1 with phase-adjustable SYSREF?

No - the SI5380A-B08455-GM supports JESD204B Subclass 0 and Subclass 1 only for phase-matched DCLK/SYSREF pairs generated from the same Multisynth. For full SYSREF phase adjustment capability, Skyworks recommends the SI5386A-D-GM. The SI5380A-B08455-GM does not provide register-controlled SYSREF delay or skew tuning.

How does the SI5380A-B08455-GM handle reference clock failure during operation?

Upon input clock failure, the SI5380A-B08455-GM automatically enters holdover mode using up to 120 seconds of averaged historical frequency data to compute a stable output frequency. The holdover exit can be ramped (default) to avoid glitches, with programmable ramp rates from 0.2 ppm/s to 40,000 ppm/s - ensuring seamless resynchronization when a valid reference returns.

What crystal specifications are required for the XA/XB pins of the SI5380A-B08455-GM?

The SI5380A-B08455-GM requires a 54 MHz fundamental-mode crystal with ±100 ppm total accuracy (including temp, voltage, aging). Internal 8 pF load capacitors eliminate external C-L components. Crystal drive level must be ≤100 µW; ESR ≤40 Ω; and shunt capacitance ≤7 pF. These specs ensure optimal phase noise and jitter performance per Skyworks Si5380 Rev D datasheet Table 5.12.

Can the SI5380A-B08455-GM operate without an external crystal?

Yes - the SI5380A-B08455-GM supports external REFCLK input (LVCMOS or differential) on XA/XB instead of a crystal, but this degrades phase noise and increases output jitter due to direct propagation of reference clock noise. The crystal option is strongly recommended for wireless infrastructure applications where <65 fs jitter and –159 dBc/Hz phase noise are required. REFCLK mode disables internal load capacitors.