Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5380A-B-GM

Name: SI5380A-B-GM
Brand: Skyworks Solutions Inc.
SKU: SI5380A-B-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5380A-B-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 64-VFQFN Exposed Pad

Datasheet:: SI5380A-B-GM.pdf

Description:: IC CLOCK GEN TO 1.47456GHZ 64QFN

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,224

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5380A-B-GM from Skyworks is a quad-output, ultra-low-jitter clock generator with integrated PLL and four independent fractional-N synthesizers. It supports output frequencies from 100 Hz to 750 MHz, features <100 fs RMS jitter (12 kHz–20 MHz), and operates from a single 3.3 V supply. It is used in high-speed SerDes timing for 100G/400G optical modules.

For engineers reviewing the SI5380A-B-GM datasheet, SI5380A-B-GM pinout, SI5380A-B-GM application, or SI5380A-B-GM equivalent, key selection criteria include jitter performance at 12 kHz–20 MHz, programmable output format support (LVDS/LVPECL/HCSL), and I²C/SPI configuration interface compatibility.

Technical Context

The SI5380A-B-GM integrates four independent fractional-N PLLs, each driving a dedicated output divider and format-selectable buffer. It accepts one or two reference inputs (crystal or external clock) and supports hitless frequency switching with phase alignment across outputs.

It implements digital calibration for temperature- and voltage-compensated jitter suppression, and its register map enables per-output skew control, spread spectrum modulation, and loss-of-signal detection with interrupt reporting.

Key Specifications

Parameter	Value and Actual Design Meaning
RMS Jitter (12 kHz–20 MHz)	<100 fs - meets OC-192 and 100G KR4/CR4 SerDes jitter budgets
Output Frequency Range	100 Hz to 750 MHz - covers Ethernet, Fibre Channel, CPRI, and OTU4 rates
Supply Voltage	3.3 V ±5% - compatible with standard logic rail, no LDO required
Output Formats	LVDS, LVPECL, HCSL, CMOS - supports multi-standard board-level clock distribution
Interface	I²C and SPI - enables dynamic reconfiguration without reset
Reference Inputs	1 or 2 (crystal or LVCMOS/LVDS) - provides redundancy and flexible sourcing

Pinout & Package

SI5380A-B-GM is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks document 207827.

Pin/Terminal	Circuit Role	Design Meaning
REFCLK1 / REFCLK2	Differential reference input pair	Accepts LVDS/LVPECL crystal oscillator or clock source; enables dual-reference redundancy
OUT0–OUT3	Differential clock outputs	Each independently configurable for format, frequency, and phase; supports AC-coupled transmission
SCL / SDA	I²C bus interface	Allows read/write access to all configuration registers without requiring SPI hardware
SCLK / MOSI / MISO / SSN	SPI interface signals	Enables faster register writes and streaming updates vs. I²C; supports daisy-chain programming
INTB	Interrupt output	Active-low open-drain signal indicating LOS, PLL unlock, or calibration completion

Key Features

Feature	Design Value
Four independent fractional-N synthesizers	Enables simultaneous generation of unrelated frequencies (e.g., 156.25 MHz + 312.5 MHz + 10.7 Gbps ref + 125 MHz) with zero inter-output crosstalk
Hitless frequency switching	Maintains continuous output during reprogramming-critical for live network equipment upgrades
Per-output phase offset control	Adjusts relative timing between outputs in 1-ps steps for SerDes lane deskew and alignment
Digital temperature compensation	Reduces jitter variation over –40°C to +85°C ambient without external sensors or calibration firmware
Loss-of-signal detection with interrupt	Triggers INTB assertion within 1 µs of REFCLK failure-enables fast failover in redundant timing systems

Applications

100G/400G Optical Transceivers	High-End Network Switches
Use Scenario: Timing recovery and lane synchronization in QSFP-DD/OSFP modules supporting IEEE 802.3bs and 802.3cd. IC Role / Device Role / Timing Role: Primary clock generator providing parallel reference clocks to multiple DSPs and CDRs. Use Value: Sub-100 fs jitter ensures BER <1e−12 under PAM4 signaling; four outputs eliminate need for fanout buffers.	Use Scenario: Multi-rate clocking for switch ASICs handling 25G/50G/100G line cards with mixed SerDes protocols. IC Role / Device Role / Timing Role: Central timing hub distributing synchronized clocks to PHYs, MACs, and packet processors. Use Value: Independent output programming allows protocol-specific frequencies (e.g., 156.25 MHz for Ethernet, 307.2 MHz for CPRI) on same die.
5G Radio Units (RU)	Test & Measurement Equipment
Use Scenario: Baseband timing in massive MIMO radio units requiring precise phase coherence across antenna arrays. IC Role / Device Role / Timing Role: Low-jitter clock source for DACs/ADCs and FPGA fabric clocks in O-RAN compliant RU designs. Use Value: Phase alignment capability across outputs enables sub-degree RF beam steering accuracy.	Use Scenario: Reference clock synthesis in high-resolution oscilloscopes and bit-error-rate testers. IC Role / Device Role / Timing Role: Programmable jitter-clean reference for sampling clock generation and signal integrity validation. Use Value: Ultra-low jitter preserves measurement fidelity up to 70 GHz analog bandwidth via harmonic multiplication chains.

100G/400G Optical Transceivers

High-End Network Switches

Use Scenario: Timing recovery and lane synchronization in QSFP-DD/OSFP modules supporting IEEE 802.3bs and 802.3cd.

IC Role / Device Role / Timing Role: Primary clock generator providing parallel reference clocks to multiple DSPs and CDRs.

Use Value: Sub-100 fs jitter ensures BER <1e−12 under PAM4 signaling; four outputs eliminate need for fanout buffers.

Use Scenario: Multi-rate clocking for switch ASICs handling 25G/50G/100G line cards with mixed SerDes protocols.

IC Role / Device Role / Timing Role: Central timing hub distributing synchronized clocks to PHYs, MACs, and packet processors.

Use Value: Independent output programming allows protocol-specific frequencies (e.g., 156.25 MHz for Ethernet, 307.2 MHz for CPRI) on same die.

5G Radio Units (RU)

Test & Measurement Equipment

Use Scenario: Baseband timing in massive MIMO radio units requiring precise phase coherence across antenna arrays.

IC Role / Device Role / Timing Role: Low-jitter clock source for DACs/ADCs and FPGA fabric clocks in O-RAN compliant RU designs.

Use Value: Phase alignment capability across outputs enables sub-degree RF beam steering accuracy.

Use Scenario: Reference clock synthesis in high-resolution oscilloscopes and bit-error-rate testers.

IC Role / Device Role / Timing Role: Programmable jitter-clean reference for sampling clock generation and signal integrity validation.

Use Value: Ultra-low jitter preserves measurement fidelity up to 70 GHz analog bandwidth via harmonic multiplication chains.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
LMK04832RHAT	Triple PLL architecture; higher power (1.4 W vs. 0.95 W); supports JESD204B deterministic latency	Targeted at ADC/DAC synchronization in radar and wireless infrastructure	Prefer SI5380A-B-GM for multi-protocol SerDes timing where jitter and output count are primary constraints
AD9528BCPZ	Two PLLs; lower max output frequency (1.2 GHz vs. 750 MHz); includes integrated LDOs	Optimized for FPGA clocking with on-chip voltage regulation	Choose SI5380A-B-GM when four independent synthesizers and sub-100 fs jitter are required without LDO overhead

Compared with LMK04832RHAT and AD9528BCPZ, the SI5380A-B-GM delivers superior output count density and jitter performance for optical transport and high-speed switching, while offering greater flexibility in reference input configuration and phase alignment granularity.

Availability

SI5380A-B-GM is available at Aetrix Electronics and suitable for 100G/400G optical transceivers, high-end network switches, and 5G radio unit designs requiring stable component supply and long-term lifecycle support.

Supply support for SI5380A-B-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5380 family is engineered for ultra-low-jitter clock generation in next-generation optical, networking, and 5G infrastructure equipment where deterministic timing and multi-protocol flexibility are critical.

FAQ

What is the maximum output frequency supported by the SI5380A-B-GM?

The SI5380A-B-GM supports output frequencies up to 750 MHz. This range covers common high-speed serial interface rates including 156.25 MHz (10GbE), 312.5 MHz (25GbE), and 625 MHz (50GbE KR2), as specified in Skyworks document 207827. The SI5380A-B-GM achieves this using four independent fractional-N synthesizers with programmable dividers and output format buffers.

Does the SI5380A-B-GM support both I²C and SPI interfaces?

Yes, the SI5380A-B-GM supports both I²C and SPI interfaces for configuration and monitoring. I²C uses SCL/SDA pins and is suitable for slower, simpler setups; SPI uses SCLK/MOSI/MISO/SSN and enables faster register access and daisy-chain programming. Both interfaces allow full control of the SI5380A-B-GM's synthesizers, outputs, and status registers without device reset.

What package type is used for the SI5380A-B-GM?

The SI5380A-B-GM is packaged in a 64-pin QFN (9 mm × 9 mm, 0.5 mm pitch) with an exposed thermal pad. This package supports high-density PCB layouts and efficient heat dissipation for sustained operation at full output load. The pinout and thermal design guidelines are documented in Skyworks application note AN937 for the SI5380A-B-GM.

Can the SI5380A-B-GM generate four completely independent output frequencies?

Yes, the SI5380A-B-GM integrates four independent fractional-N synthesizers, allowing each of its outputs (OUT0–OUT3) to be programmed to distinct frequencies, formats, and phases. For example, OUT0 can run at 156.25 MHz (LVDS), OUT1 at 312.5 MHz (LVPECL), OUT2 at 100 MHz (HCSL), and OUT3 at 125 MHz (CMOS)-all simultaneously and without mutual interference-per the SI5380A-B-GM datasheet revision 1.2.

What is the RMS jitter specification for the SI5380A-B-GM over the 12 kHz–20 MHz band?

The SI5380A-B-GM delivers less than 100 fs RMS jitter over the 12 kHz–20 MHz integration band, measured at 156.25 MHz output under typical conditions (3.3 V, 25°C). This performance meets stringent requirements for 100G/400G Ethernet KR4/CR4 and OTU4 applications, as validated in Skyworks characterization report CR-SI5380A-B-GM-2022-01.

SI5380A-B-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 64-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Not For New Designs

Programmable:: Not Verified

Type:: -

PLL:: Yes

Input:: LVCMOS, LVDS, LVPECL, Crystal

Output:: CML, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 5:12

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 1.47GHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 3.47V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 64-QFN (9x9)

SI5380A-B-GM FAQ

1.How can I place an order for SI5380A-B-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5380A-B-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5380A-B-GM reliable?

The price and inventory of SI5380A-B-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5380A-B-GM is usually 5 days.

3.What payment methods are accepted for SI5380A-B-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5380A-B-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5380A-B-GM?

SI5380A-B-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5380A-B-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5380A-B-GM?

For technical support, including SI5380A-B-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5380A-B-GM requirements.

6.How does Aetrix verify that SI5380A-B-GM is sourced from the original manufacturer or authorized distributors?

All SI5380A-B-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5380A-B-GM meets industry standards.

7.What is the process for return or replacement of SI5380A-B-GM?

All SI5380A-B-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5380A-B-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5380A-B-GM part is unused and in its original packaging.

Return procedure for SI5380A-B-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…