Skyworks Solutions Inc. SI5380A-C-GM

Overview

SI5380A-C-GM from Skyworks Solutions is a 12-output, integer-based JESD204B jitter attenuator and clock multiplexer optimized for wireless small cell infrastructure. It integrates DSPLL™ technology to deliver ultra-low phase noise (–159 dBc/Hz floor), 65 fs RMS jitter (12 kHz–20 MHz), and supports both DCLK and SYSREF generation for Subclass 0/1 applications. Its 4-input, 12-output architecture enables synchronized clock distribution in remote radio units and LTE-A base stations.

For engineers reviewing the SI5380A-C-GM datasheet, SI5380A-C-GM pinout, SI5380A-C-GM application, or SI5380A-C-GM equivalent, this page provides verified technical context, validated pin functions, confirmed JESD204B timing compliance, real-world holdover behavior, and alternative selection guidance grounded in Skyworks' official Rev D documentation and ordering guide.

Technical Context

The SI5380A-C-GM implements Skyworks' 4th-generation DSPLL architecture with a 15 GHz VCO, programmable digital loop filter (0.1 Hz–100 Hz bandwidth), and integrated 54 MHz crystal oscillator interface. It eliminates external VCXO and analog loop filter components while maintaining frequency stability across freerun, locked, and holdover modes.

It supports hitless and ramped input switching between four clock sources (IN0–IN3), configurable output dividers (R), and independent output supply pins (1.8 V/2.5 V/3.3 V). Status monitoring includes LOS, OOF, and LOL detection, with interrupt signaling via INTRb and LOLb pins.

Key Specifications

Pinout & Package

SI5380A-C-GM is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev D datasheet Section 9 (Pin Description) and validated against Figure 3.3 (XA/XB connections) and Figure 3.4 (INx termination).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Compared with SI5380A-C-GM, Si5386A-D-GM adds essential phase-adjust features for advanced JESD204B systems, while LMK04832ISQE/NOPB trades integration for marginally lower jitter-making SI5380A-C-GM the optimal balance of performance, simplicity, and wireless infrastructure readiness.

Availability

SI5380A-C-GM is available at Aetrix Electronics and suitable for remote radio units, small cell base stations, and wireless backhaul systems requiring stable component supply with long-term lifecycle support.

Supply support for SI5380A-C-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, and industrial markets.

The SI5380A-C-GM belongs to Skyworks' Si5380 family of wireless jitter attenuators, designed specifically for high-integration, ultra-low-phase-noise clocking in 3G/4G/LTE-A and 5G small cell infrastructure.

FAQ

What is the primary function of the SI5380A-C-GM in wireless infrastructure?

The SI5380A-C-GM serves as a 12-output jitter attenuator and clock multiplexer that synthesizes ultra-low-jitter clocks for JESD204B data converters and baseband processors in remote radio units and small cells. Its DSPLL architecture eliminates external VCXO and loop filter components while delivering 65 fs RMS jitter and –159 dBc/Hz phase noise floor-critical for maintaining signal integrity in high-order modulation schemes used in LTE-A and 5G NR.

Does the SI5380A-C-GM support JESD204B Subclass 1 with phase adjustment between DCLK and SYSREF?

No-the SI5380A-C-GM supports JESD204B Subclass 0 and Subclass 1 DCLK/SYSREF generation only when phase matching is required. It does not provide programmable phase offset between DCLK and SYSREF. For applications requiring adjustable phase alignment (e.g., multi-device synchronization), Skyworks recommends the SI5386A-D-GM, which explicitly adds DCLK–SYSREF phase tuning capability per its Rev D datasheet Section 3.1.2.

How does the SI5380A-C-GM handle clock source failure in a redundant system?

Upon failure of the selected input clock, the SI5380A-C-GM automatically enters holdover mode using an averaged frequency derived from up to 120 seconds of prior locked-history data. This averaged value minimizes phase disturbance at the outputs. The device exits holdover glitchlessly when a valid clock returns, optionally ramping the output frequency at a user-configurable rate (0.2–40,000 ppm/s) to avoid transient overshoot-details confirmed in Sections 3.1.10 and Figure 3.2 of the SI5380 Rev D datasheet.

What crystal specifications are required for the XA/XB pins on the SI5380A-C-GM?

The SI5380A-C-GM requires a 54 MHz fundamental-mode crystal with total accuracy of ±100 ppm (including initial tolerance, temperature, voltage, load, and aging effects). Internal 8 pF load capacitors eliminate need for external caps. Crystal drive level must be ≤100 µW; ESR ≤40 Ω; shunt capacitance ≤7 pF. These values are specified in Table 5.12 of the SI5380 Rev D datasheet and validated for optimal jitter performance in wireless infrastructure applications.

Is the SI5380A-C-GM pin-compatible with other variants in the Si5380 family, such as SI5380A-D-GM?

Yes-SI5380A-C-GM and SI5380A-D-GM share identical 64-QFN 9×9 mm packaging, pinout, and electrical interface. The "C" and "D" suffixes denote different silicon revisions (Rev C vs Rev D), with Rev D introducing minor errata fixes and updated characterization. All register maps, configuration sequences, and functional behavior remain backward-compatible per Skyworks' ordering guide and revision history (Section 14, Rev D datasheet).