Skyworks Solutions Inc. SI5380A-D07544-GM

Overview

SI5380A-D07544-GM from Skyworks Solutions is a 12-output, integer-based JESD204B jitter attenuator and clock multiplexer optimized for wireless infrastructure. It delivers ultra-low phase noise (–159 dBc/Hz floor), 65 fs RMS jitter (12 kHz–20 MHz), and supports DCLK/SYSREF generation with hitless switching across four inputs. It operates in freerun, locked, and holdover modes using a 54 MHz crystal reference and targets small cell RRU and LTE-A base station timing.

For engineers reviewing the SI5380A-D07544-GM datasheet, SI5380A-D07544-GM pinout, SI5380A-D07544-GM application, or SI5380A-D07544-GM equivalent, key selection criteria include JESD204B Subclass 0/1 SYSREF phase matching, DSPLL loop bandwidth configurability (0.1 Hz–100 Hz), output skew ≤65 ps (same N-divider), differential output range up to 1.47456 GHz, and factory preprogrammed configuration support via ClockBuilder Pro.

Technical Context

The SI5380A-D07544-GM implements Skyworks' 4th-generation DSPLL architecture with a 15 GHz VCO, programmable digital loop filter, and integrated 54 MHz crystal oscillator-eliminating external VCXO and analog loop filter components. Its all-digital synthesis path provides immunity to power supply noise and board-level disturbances.

It supports automatic input qualification, hitless and ramped clock switching between IN0–IN3, and configurable holdover using 120-second frequency history averaging. Output dividers (R) and multisynths enable up to 10 unique integer-ratio frequencies distributed across 12 outputs with independent voltage supply pins (1.8 V/2.5 V/3.3 V).

Key Specifications

Pinout & Package

The SI5380A-D07544-GM is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5380 Rev D datasheet Section 9 (Pin Description) and Figure 3.3 (XA/XB connections).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Compared with SI5380A-D07544-GM, the Si5386A-D08589-GM adds essential phase-adjustable SYSREF for advanced 5G beamforming, while the LTC6957IUF-3#PBF trades digital flexibility and wireless-specific features for analog simplicity and lower component count in non-infrastructure applications.

Availability

SI5380A-D07544-GM is available at Aetrix Electronics and suitable for wireless infrastructure, remote radio units, and JESD204B data converter timing requiring stable component supply and long-term lifecycle support.

Supply support for SI5380A-D07544-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a U.S.-based semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, automotive, and industrial markets.

The SI5380A-D07544-GM belongs to Skyworks' Si5380 family of wireless jitter attenuators-designed specifically for high-density, low-jitter clock generation in 3G/4G/5G small cell and macro base station applications.

FAQ

What is the primary function of the SI5380A-D07544-GM in wireless infrastructure systems?

The SI5380A-D07544-GM serves as a 12-output JESD204B jitter attenuator and clock multiplexer, generating ultra-low-jitter DCLK and SYSREF signals for ADCs, DACs, and FPGAs in RRUs and small cells. Its DSPLL architecture eliminates external VCXOs and analog filters, and it supports freerun, locked, and holdover modes using a 54 MHz crystal-making SI5380A-D07544-GM ideal for timing-critical wireless baseband and RF subsystems.

Does the SI5380A-D07544-GM support JESD204B Subclass 1 with adjustable SYSREF phase?

No. The SI5380A-D07544-GM supports JESD204B Subclass 0 and Subclass 1 only for phase-matched DCLK/SYSREF pairs generated from the same Multisynth. It does not provide programmable phase offset between DCLK and SYSREF. For adjustable SYSREF phase, Skyworks recommends the Si5386A-D08589-GM. This limitation is explicitly documented in the SI5380 Rev D datasheet Section 3.1.2.

What is the role of the XA/XB pins on the SI5380A-D07544-GM?

The XA/XB pins on the SI5380A-D07544-GM form a differential interface for a 54 MHz fundamental-mode crystal, which feeds the internal oscillator (OSC) used by the DSPLL for freerun and holdover modes. The device integrates 8 pF load capacitors, eliminating external components. Using XA/XB with a crystal-not an external XO-is recommended to achieve the specified 65 fs jitter and –159 dBc/Hz phase noise floor for SI5380A-D07544-GM.

How does hitless switching work on the SI5380A-D07544-GM, and when is it applicable?

Hitless switching on the SI5380A-D07544-GM prevents phase transients during input clock switchover by absorbing the fixed phase difference between two frequency-locked inputs (e.g., identical 122.88 MHz references). It requires exact frequency match or integer ratio and is enabled via register configuration. This feature ensures uninterrupted timing in RAN systems during reference failover-unlike glitchless switching, which propagates phase error at the DSPLL loop bandwidth rate.

Is the SI5380A-D07544-GM suitable for new designs, and what is its lifecycle status?

No-the SI5380A-D07544-GM is marked "Not Recommended for New Designs" per the official Skyworks Si5380 Rev D datasheet. It remains available for existing production and legacy support, but Skyworks recommends the Si5386 family for new wireless infrastructure designs due to enhanced JESD204B Subclass 1 capabilities and extended feature set. Customers designing new systems should evaluate SI5380A-D07544-GM only for continuity or cost-sensitive refresh projects.