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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5380A-D07753-GM

Name: SI5380A-D07753-GM
Brand: Skyworks Solutions Inc.
SKU: SI5380A-D07753-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5380A-D07753-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5380A-D07753-GM.pdf

Description:: IC CLOCK GENERATOR

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Product details

Overview

SI5380A-D07753-GM from Skyworks Solutions is a 12-output, integer-based JESD204B jitter attenuator and clock multiplexer optimized for wireless small cell infrastructure. It delivers ultra-low phase noise (–159 dBc/Hz floor), 65 fs RMS jitter (12 kHz–20 MHz), and supports DCLK/SYSREF generation with hitless switching across four differential or LVCMOS inputs. Its DSPLL architecture eliminates external VCXO and analog loop filter components, enabling robust clock synthesis in RRU and picocell baseband timing applications.

For engineers reviewing the SI5380A-D07753-GM datasheet, SI5380A-D07753-GM pinout, SI5380A-D07753-GM application, or SI5380A-D07753-GM equivalent, this page provides verified technical context on DSPLL loop bandwidth (0.1 Hz–100 Hz), output skew (≤65 ps), configurable common-mode voltage, LVCMOS/LVDS/LVPECL compatibility, and factory pre-programmed JESD204B LTE frequency support - all critical for 4G/LTE-A and 5G NR fronthaul timing design.

Technical Context

The SI5380A-D07753-GM implements Skyworks' 4th-generation DSPLL with a 15 GHz VCO, programmable digital loop filter, and integrated 54 MHz crystal oscillator. It synthesizes up to 10 integer-related frequencies across 12 outputs using N- and R-dividers, with independent output supply pins (1.8 V/2.5 V/3.3 V) and configurable output swing (200–3200 mVpp).

It operates in four deterministic modes: freerun (crystal-referenced), lock acquisition (with Fastlock bandwidth up to 4 kHz), locked (jitter attenuation enabled), and holdover (averaged historical frequency retention up to 120 s). Input fault monitoring includes LOS, OOF, and LOL detection, with interrupt-driven status reporting via INTRb pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (RMS)	65 fs (12 kHz–20 MHz); enables JESD204B Subclass 0/1 compliance for high-speed ADC/DAC sampling clocks
Phase Noise Floor	–159 dBc/Hz; ensures minimal spectral contamination in RF transceiver local oscillator paths
Input Range	Differential: 11.52–737.28 MHz; LVCMOS: 11.52–245.76 MHz - covers all LTE/5G carrier and reference frequencies
Output Range	Differential: 480 kHz–1.47456 GHz; LVCMOS: 480 kHz–245.76 MHz - supports DCLK (e.g., 122.88 MHz, 245.76 MHz) and SYSREF
DSPLL Loop BW	0.1–100 Hz (register-configurable); determines jitter attenuation depth without stability risk (<0.1 dB peaking)
Output Skew	≤65 ps max (same N-divider); guarantees tight inter-channel timing alignment for multi-antenna beamforming systems
Core Voltage	VDD = 1.8 V ±5%; VDDA = 3.3 V ±5% - enables low-power operation while maintaining analog performance

Pinout & Package

SI5380A-D07753-GM is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5380 Rev D datasheet Section 9 (Pin Description) and Figure 3.3 (XA/XB crystal interface).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Primary clock inputs	Support differential (LVDS/LVPECL/CML) or single-ended LVCMOS; IN3 serves as FB_IN when zero-delay mode enabled
XA/XB	Crystal oscillator terminals	Accept 54 MHz fundamental-mode crystal (±100 ppm); internal 8 pF load caps eliminate external capacitors
OUT0–OUT11	Programmable clock outputs	Configurable signal format (LVDS/LVPECL/LVCMOS), swing (200–3200 mVpp), and common-mode voltage
INTRb	Interrupt output	Active-low open-drain flag indicating LOS/OOF/LOL events; enables real-time system fault response
PDNb	Power-down control	Active-low input that places device in low-power state while preserving register contents and NVM configuration
I2C/SPI	Configuration interface	Two-wire I²C or 4-wire SPI for in-circuit programming; non-volatile OTP memory retains factory settings

Key Features

Feature	Design Value
DSPLL-based jitter attenuation	Eliminates external VCXO and analog loop filter - reduces BOM count, PCB area, and sensitivity to power supply noise
JESD204B DCLK/SYSREF support	Enables phase-matched clock pairs from same Multisynth; meets Subclass 0/1 timing requirements for data converter synchronization
Hitless input switching	Prevents phase transients during clock source failover between frequency-locked inputs - maintains deterministic latency in RAN systems
Programmable holdover	Uses 120-second frequency history window to compute stable holdover frequency - minimizes phase jump during input loss in remote radio units
Independent output supplies	Per-output VDDO pins (1.8 V/2.5 V/3.3 V) allow mixed-signal SoC interfacing without level-shifting components

Applications

Remote Radio Unit (RRU) Timing	Small Cell Baseband Clocking
Use Scenario: Synchronizing multiple transceivers and FPGAs in distributed antenna systems with strict phase coherence requirements. IC Role / Device Role / Timing Role: Primary jitter-attenuated clock generator providing DCLK and SYSREF to JESD204B-compliant ADCs/DACs and digital front-end processors. Use Value: 65 fs jitter and ≤65 ps output skew ensure sub-sample timing alignment across parallel RF chains for MIMO beamforming.	Use Scenario: Generating multiple synchronized clocks for LTE-A and 5G NR small cell baseband processing, including FPGA fabric, memory interfaces, and PHY layer logic. IC Role / Device Role / Timing Role: Integrated clock multiplexer and jitter cleaner replacing discrete PLL + VCXO + fanout buffer solutions. Use Value: DSPLL architecture eliminates analog loop filter tuning and external VCXO, reducing design cycle time and field failure risk from component drift.
Wireless Backhaul Synchronization	ADC/DAC Sampling Clock Generation
Use Scenario: Maintaining precise frequency and phase alignment across microwave or millimeter-wave backhaul links operating in holdover during GPS/GNSS outage. IC Role / Device Role / Timing Role: Holdover-stabilized clock source using averaged historical frequency data and 54 MHz crystal reference. Use Value: Programmable 120-second holdover history window and ramped exit reduce frequency pull-in transients by >90% versus fixed-frequency XO alternatives.	Use Scenario: Providing low-jitter sampling clocks to high-resolution ADCs (e.g., 16-bit, 250 MSPS) and DACs in software-defined radios and test equipment. IC Role / Device Role / Timing Role: Ultra-low phase noise clock generator with –159 dBc/Hz floor and <–103 dBc spurs at 122.88 MHz carrier. Use Value: Enables ENOB >14.2 bits at Nyquist for wideband receivers by minimizing aperture jitter-induced SNR degradation.

Remote Radio Unit (RRU) Timing

Small Cell Baseband Clocking

Use Scenario: Synchronizing multiple transceivers and FPGAs in distributed antenna systems with strict phase coherence requirements.

IC Role / Device Role / Timing Role: Primary jitter-attenuated clock generator providing DCLK and SYSREF to JESD204B-compliant ADCs/DACs and digital front-end processors.

Use Value: 65 fs jitter and ≤65 ps output skew ensure sub-sample timing alignment across parallel RF chains for MIMO beamforming.

Use Scenario: Generating multiple synchronized clocks for LTE-A and 5G NR small cell baseband processing, including FPGA fabric, memory interfaces, and PHY layer logic.

IC Role / Device Role / Timing Role: Integrated clock multiplexer and jitter cleaner replacing discrete PLL + VCXO + fanout buffer solutions.

Use Value: DSPLL architecture eliminates analog loop filter tuning and external VCXO, reducing design cycle time and field failure risk from component drift.

Wireless Backhaul Synchronization

ADC/DAC Sampling Clock Generation

Use Scenario: Maintaining precise frequency and phase alignment across microwave or millimeter-wave backhaul links operating in holdover during GPS/GNSS outage.

IC Role / Device Role / Timing Role: Holdover-stabilized clock source using averaged historical frequency data and 54 MHz crystal reference.

Use Value: Programmable 120-second holdover history window and ramped exit reduce frequency pull-in transients by >90% versus fixed-frequency XO alternatives.

Use Scenario: Providing low-jitter sampling clocks to high-resolution ADCs (e.g., 16-bit, 250 MSPS) and DACs in software-defined radios and test equipment.

IC Role / Device Role / Timing Role: Ultra-low phase noise clock generator with –159 dBc/Hz floor and <–103 dBc spurs at 122.88 MHz carrier.

Use Value: Enables ENOB >14.2 bits at Nyquist for wideband receivers by minimizing aperture jitter-induced SNR degradation.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5386A-D08581-GM	Supports JESD204B Subclass 1 with programmable DCLK–SYSREF phase offset; higher integration of dual DSPLL cores	Required for phase-adjustable SYSREF in advanced radar and phased-array systems where deterministic latency calibration is needed	Select Si5386A-D08581-GM only if phase adjustment between DCLK and SYSREF is mandatory; otherwise SI5380A-D07753-GM offers lower cost and sufficient performance for LTE/4G RRU
LTC6957IUF-3#PBF	Analog PLL-based jitter cleaner; 225 fs RMS jitter (12 kHz–20 MHz); no integrated crystal oscillator or NVM	Suitable for legacy systems requiring analog loop tuning or where external VCXO is already deployed	Choose LTC6957IUF-3#PBF only when retrofitting existing analog PLL designs; SI5380A-D07753-GM provides superior jitter, digital configurability, and reduced component count

Compared with Si5386A-D08581-GM, SI5380A-D07753-GM lacks programmable DCLK–SYSREF phase offset but delivers identical jitter and holdover performance at lower cost and complexity. Versus LTC6957IUF-3#PBF, it replaces analog loop design effort with digital configuration, integrates crystal support, and achieves 3.5× lower RMS jitter - directly improving ADC ENOB in wideband receivers.

Availability

SI5380A-D07753-GM is available at Aetrix Electronics and suitable for wireless infrastructure, remote radio unit timing, and JESD204B data converter clocking requiring stable component supply and long-term lifecycle support.

Supply support for SI5380A-D07753-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5380 product line was designed specifically for high-integration, ultra-low-jitter clock generation in wireless infrastructure - addressing the phase noise, holdover stability, and JESD204B timing demands of 4G/LTE-A and early 5G NR small cells.

FAQ

What is the primary function of the SI5380A-D07753-GM in wireless infrastructure systems?

The SI5380A-D07753-GM serves as a 12-output jitter attenuator and clock multiplexer, generating ultra-low-jitter DCLK and SYSREF signals for JESD204B-compliant ADCs/DACs in RRUs and small cells. Its DSPLL architecture synthesizes integer-related frequencies from up to four inputs while attenuating incoming jitter - eliminating need for external VCXO and analog loop filters. This makes SI5380A-D07753-GM ideal for timing-critical 4G/LTE-A baseband processing.

Does the SI5380A-D07753-GM support JESD204B Subclass 1 with phase-adjustable SYSREF?

No, the SI5380A-D07753-GM supports JESD204B Subclass 0 and Subclass 1 only for phase-matched DCLK/SYSREF pairs generated from the same Multisynth. It does not provide programmable phase offset between DCLK and SYSREF. For applications requiring adjustable SYSREF phase (e.g., advanced radar calibration), Skyworks recommends the Si5386A-D08581-GM instead. SI5380A-D07753-GM remains optimal for LTE/4G RRU where matched-phase timing suffices.

What crystal specifications are required for the SI5380A-D07753-GM XA/XB interface?

The SI5380A-D07753-GM requires a 54 MHz fundamental-mode crystal with total accuracy of ±100 ppm (including initial tolerance, temperature, voltage, load, and aging effects). Internal 8 pF load capacitors eliminate need for external capacitors. The crystal must be connected directly to XA/XB pins with minimal trace length and proper grounding per Skyworks Reference Manual guidelines to achieve specified 65 fs jitter. Using an external XO instead of crystal increases output jitter and is not recommended for SI5380A-D07753-GM deployments targeting lowest phase noise.

How does the SI5380A-D07753-GM handle clock input failure in remote radio units?

Upon input failure, the SI5380A-D07753-GM automatically enters holdover mode using up to 120 seconds of stored frequency history to compute a stable averaged holdover frequency. This minimizes phase disturbance at outputs during GPS/GNSS outages common in remote radio units. Holdover exit can be ramped (default) using user-selectable rates (0.2–40,000 ppm/s) to avoid frequency transients - a key reliability feature confirmed in SI5380A-D07753-GM's functional description and validated in Skyworks AN1165.

Is the SI5380A-D07753-GM pin-compatible with other Si5380 variants like SI5380A-D-GM?

Yes, SI5380A-D07753-GM shares the identical 64-QFN 9×9 mm package and pinout with all Si5380A-D-x-GM variants, including SI5380A-D-GM. The "D07753" suffix denotes a factory pre-programmed configuration optimized for specific LTE/JESD204B frequency sets, but electrical and mechanical interfaces remain fully compatible. This allows drop-in replacement in existing layouts - provided firmware and register initialization match the pre-programmed profile of SI5380A-D07753-GM.

SI5380A-D07753-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tray

Product Status:: Not For New Designs

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

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SI5380A-D07753-GM FAQ

1.How can I place an order for SI5380A-D07753-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5380A-D07753-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5380A-D07753-GM reliable?

The price and inventory of SI5380A-D07753-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5380A-D07753-GM is usually 5 days.

3.What payment methods are accepted for SI5380A-D07753-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5380A-D07753-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5380A-D07753-GM?

SI5380A-D07753-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5380A-D07753-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5380A-D07753-GM?

For technical support, including SI5380A-D07753-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5380A-D07753-GM requirements.

6.How does Aetrix verify that SI5380A-D07753-GM is sourced from the original manufacturer or authorized distributors?

All SI5380A-D07753-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5380A-D07753-GM meets industry standards.

7.What is the process for return or replacement of SI5380A-D07753-GM?

All SI5380A-D07753-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5380A-D07753-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5380A-D07753-GM part is unused and in its original packaging.

Return procedure for SI5380A-D07753-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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