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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5380A-D08067-GM

Name: SI5380A-D08067-GM
Brand: Skyworks Solutions Inc.
SKU: SI5380A-D08067-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5380A-D08067-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5380A-D08067-GM.pdf

Description:: IC CLOCK GENERATOR

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Product details

Overview

SI5380A-D08067-GM from Skyworks Solutions is a 12-output, integer-based JESD204B jitter attenuator and clock multiplexer optimized for wireless small cell infrastructure. It delivers ultra-low phase noise (–159 dBc/Hz floor), 65 fs RMS jitter (12 kHz–20 MHz), and supports DCLK/SYSREF generation with hitless switching across four differential or LVCMOS inputs. Its DSPLL architecture eliminates external VCXO and analog loop filters, enabling robust clock synthesis in RRU and picocell baseband timing applications.

For engineers reviewing the SI5380A-D08067-GM datasheet, SI5380A-D08067-GM pinout, SI5380A-D08067-GM application, or SI5380A-D08067-GM equivalent, this page provides verified technical context, real-world use cases, validated alternatives, and supply-chain support tailored to LTE/LTE-A and JESD204B data converter timing systems.

Technical Context

The SI5380A-D08067-GM implements Skyworks' 4th-generation DSPLL with a 15 GHz VCO, programmable digital loop filter (0.1 Hz–100 Hz bandwidth), and integrated 54 MHz crystal oscillator. It operates in freerun, locked, holdover, and fast-lock acquisition modes - all managed autonomously without host intervention.

Its 12 outputs support independent configuration: differential (LVDS/LVPECL) up to 1.47456 GHz or LVCMOS up to 245.76 MHz, with output skew ≤65 ps (same N-divider), configurable common-mode voltage, and synchronous enable/disable. Input monitoring includes LOS, OOF, and LOL detection with interrupt signaling via INTRb.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (RMS)	65 fs (12 kHz–20 MHz); enables sub-16-bit ADC/DAC sampling integrity in JESD204B Subclass 0/1 systems
Phase Noise Floor	–159 dBc/Hz; critical for EVM-sensitive LTE-A carrier aggregation and massive MIMO RF front-ends
Output Count	12 configurable outputs; supports full JESD204B lane clocking + SYSREF + auxiliary system clocks in single-chip solution
Input Range	Differential: 11.52–737.28 MHz; LVCMOS: 11.52–245.76 MHz - covers all standard LTE, W-CDMA, and 5G NR reference frequencies
Output Range	Differential: 480 kHz–1.47456 GHz; LVCMOS: 480 kHz–245.76 MHz - matches JESD204B DCLK (e.g., 122.88, 245.76, 491.52 MHz) and SYSREF requirements
Core Voltage	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%; enables low-power, thermally stable operation in dense RAN board layouts
Package	64-QFN, 9×9 mm, 0.5 mm pitch; compatible with standard SMT reflow and supports high-density RF-adjacent placement

Pinout & Package

SI5380A-D08067-GM uses a 64-pin QFN package (9×9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev D datasheet Section 9 (Pin Description) and include dedicated input selection, status monitoring, and per-output power supply pins.

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Primary clock inputs	Support differential (LVDS/LVPECL/CML) or single-ended LVCMOS; IN3 serves as FB_IN when zero-delay mode enabled
XA/XB	Crystal oscillator interface	Accepts 54 MHz fundamental-mode crystal; internal 8 pF load caps eliminate external capacitors and reduce noise coupling
OUT0–OUT11	Configurable clock outputs	Each supports independent format (LVDS/LVPECL/LVCMOS), swing (200–3200 mVpp), and supply voltage (1.8/2.5/3.3 V)
INTRb	Interrupt output	Active-low open-drain flag indicating LOS/OOF/LOL events; enables real-time fault response in RAN control firmware
PDNb	Power-down control	Hardware pin to place device in low-power state; retains register settings and NVM configuration during sleep
I2C/SPI	Configuration interface	Two-wire I²C or 4-wire SPI for in-circuit programming; supports factory pre-programming via ClockBuilder Pro OTP memory

Key Features

Feature	Design Value
DSPLL jitter attenuation	Eliminates external VCXO and analog loop filter components - reduces BOM count by ≥4 parts and improves layout immunity to PSRR noise
JESD204B DCLK/SYSREF support	Generates phase-matched DCLK/SYSREF pairs from same Multisynth - satisfies Subclass 1 deterministic latency requirements without external alignment logic
Hitless input switching	Prevents phase transients during clock source failover between frequency-locked inputs - maintains continuous data capture in ADC/DAC chains
Programmable holdover	Uses 120-second averaged historical frequency data to minimize output drift during input loss - sustains <±1 ppm accuracy for >10 seconds in RRU holdover scenarios
Zero-delay mode	Configures IN3 as feedback input to align output phase with selected input - enables precise timing alignment in distributed clock trees

Applications

Remote Radio Unit (RRU) Timing	JESD204B Data Converter Clocking
Use Scenario: Synchronizing multiple transceiver ICs and ADC/DACs in a compact RRU module with shared backhaul interface. IC Role / Device Role / Timing Role: Primary jitter-attenuated clock source generating DCLK, SYSREF, and local FPGA clocks from a single 122.88 MHz reference. Use Value: 65 fs jitter ensures <–80 dBc SFDR in 16-bit ADCs; DSPLL holdover maintains timing continuity during fronthaul link interruption.	Use Scenario: Providing deterministic, low-jitter sampling clocks to multi-channel high-speed ADCs and DACs in software-defined radio (SDR) platforms. IC Role / Device Role / Timing Role: JESD204B-compliant clock generator delivering phase-aligned DCLK/SYSREF pairs with <100 ps inter-lane skew. Use Value: Ultra-low phase noise (–159 dBc/Hz) prevents reciprocal mixing in wideband receivers; hitless switching avoids data corruption during reference switchover.
Small Cell Base Station	Wireless Backhaul Synchronization
Use Scenario: Timing engine for LTE-A picocell baseband processing, supporting carrier aggregation and MIMO signal paths. IC Role / Device Role / Timing Role: Multi-output clock synthesizer generating 30.72 MHz, 122.88 MHz, and 245.76 MHz clocks for BBIC, RFIC, and fronthaul PHY layers. Use Value: 12 outputs eliminate need for clock fanout buffers; LVCMOS/LVDS dual-format outputs simplify interface to mixed-voltage SoCs and FPGAs.	Use Scenario: Maintaining frequency and phase coherence across microwave/E-band backhaul radios operating in GPS-denied environments. IC Role / Device Role / Timing Role: Holdover-stabilized clock source using internal 54 MHz crystal to sustain <±50 ppb accuracy for >30 seconds after GNSS signal loss. Use Value: Programmable holdover window and ramped exit ensure seamless transition between GNSS and crystal-referenced operation - no packet loss or sync alarms.

Remote Radio Unit (RRU) Timing

JESD204B Data Converter Clocking

Use Scenario: Synchronizing multiple transceiver ICs and ADC/DACs in a compact RRU module with shared backhaul interface.

IC Role / Device Role / Timing Role: Primary jitter-attenuated clock source generating DCLK, SYSREF, and local FPGA clocks from a single 122.88 MHz reference.

Use Value: 65 fs jitter ensures <–80 dBc SFDR in 16-bit ADCs; DSPLL holdover maintains timing continuity during fronthaul link interruption.

Use Scenario: Providing deterministic, low-jitter sampling clocks to multi-channel high-speed ADCs and DACs in software-defined radio (SDR) platforms.

IC Role / Device Role / Timing Role: JESD204B-compliant clock generator delivering phase-aligned DCLK/SYSREF pairs with <100 ps inter-lane skew.

Use Value: Ultra-low phase noise (–159 dBc/Hz) prevents reciprocal mixing in wideband receivers; hitless switching avoids data corruption during reference switchover.

Small Cell Base Station

Wireless Backhaul Synchronization

Use Scenario: Timing engine for LTE-A picocell baseband processing, supporting carrier aggregation and MIMO signal paths.

IC Role / Device Role / Timing Role: Multi-output clock synthesizer generating 30.72 MHz, 122.88 MHz, and 245.76 MHz clocks for BBIC, RFIC, and fronthaul PHY layers.

Use Value: 12 outputs eliminate need for clock fanout buffers; LVCMOS/LVDS dual-format outputs simplify interface to mixed-voltage SoCs and FPGAs.

Use Scenario: Maintaining frequency and phase coherence across microwave/E-band backhaul radios operating in GPS-denied environments.

IC Role / Device Role / Timing Role: Holdover-stabilized clock source using internal 54 MHz crystal to sustain <±50 ppb accuracy for >30 seconds after GNSS signal loss.

Use Value: Programmable holdover window and ramped exit ensure seamless transition between GNSS and crystal-referenced operation - no packet loss or sync alarms.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5386A-D06871-GM	Supports JESD204B Subclass 1 with programmable DCLK–SYSREF phase offset; higher integration (16 outputs); newer revision with extended holdover algorithms	Required for applications needing dynamic SYSREF phase adjustment (e.g., beamforming calibration cycles)	Select Si5386A-D06871-GM when phase-adjustable SYSREF or >12 outputs are mandatory; not drop-in due to different register map and pinout
LTC6957IUF-3#PBF	Analog PLL-based jitter cleaner; 50 fs typical jitter; 4 outputs; requires external loop filter and VCXO; no integrated crystal oscillator	Better suited for low-channel-count, ultra-low-jitter legacy designs where DSPLL digital artifacts must be avoided	Choose LTC6957IUF-3#PBF only if analog PLL behavior is explicitly required; adds ≥3 external components and increases layout sensitivity

Compared with SI5380A-D08067-GM, the Si5386A-D06871-GM offers enhanced JESD204B flexibility but requires redesign, while the LTC6957IUF-3#PBF trades integration and holdover autonomy for marginal jitter reduction at higher design complexity.

Availability

SI5380A-D08067-GM is available at Aetrix Electronics and suitable for wireless infrastructure, JESD204B data converter timing, and small cell base station applications requiring stable component supply and long-term lifecycle support.

Supply support for SI5380A-D08067-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for wireless infrastructure and mobile markets.

The SI5380 family was designed specifically for high-integration, ultra-low-jitter clocking in 3G/4G/5G wireless base stations - addressing phase noise, holdover stability, and JESD204B compliance in a single-chip DSPLL architecture.

FAQ

Is SI5380A-D08067-GM recommended for new designs?

No - Skyworks marks SI5380A-D08067-GM as "Not Recommended for New Designs" per its Rev D datasheet. It remains fully supported for existing production and legacy refreshes, but new projects should evaluate the Si5386A-D series for improved JESD204B Subclass 1 features and extended lifecycle. SI5380A-D08067-GM continues to ship with full datasheet compliance and Aetrix's long-term supply assurance.

What crystal specifications are required for SI5380A-D08067-GM?

SI5380A-D08067-GM requires a 54 MHz fundamental-mode crystal with ±100 ppm total accuracy (including temp, voltage, aging), 8 pF load capacitance, and low ESR (<40 Ω). The device integrates internal 8 pF load caps - no external capacitors needed. Crystal layout must follow Skyworks Reference Manual guidelines to maintain <65 fs jitter performance.

Does SI5380A-D08067-GM support JESD204B Subclass 1 with deterministic latency?

SI5380A-D08067-GM supports JESD204B Subclass 1 only for phase-matched DCLK/SYSREF pairs generated from the same Multisynth. It does not support programmable DCLK–SYSREF phase offset. For full Subclass 1 deterministic latency with adjustable phase, Skyworks recommends the Si5386A-D06871-GM as the designated upgrade path.

How does SI5380A-D08067-GM handle input clock failure in a wireless base station?

Upon input failure, SI5380A-D08067-GM automatically enters holdover mode using a programmable 120-second history buffer. It calculates an averaged holdover frequency from a user-defined window to minimize phase disturbance. Outputs remain stable within ±1 ppm for >10 seconds - sufficient for RRU fronthaul recovery protocols - and resume lock seamlessly when input returns.

Can SI5380A-D08067-GM generate both LVDS and LVCMOS outputs simultaneously?

Yes - SI5380A-D08067-GM supports mixed-signal outputs: any of its 12 outputs can be independently configured as LVDS, LVPECL, or LVCMOS (1.8 V/2.5 V/3.3 V). Each output has dedicated VDDO pins, enabling concurrent generation of differential clocks for RFICs and single-ended clocks for FPGAs or baseband processors on the same board.

SI5380A-D08067-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tray

Product Status:: Not For New Designs

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5380A-D08067-GM FAQ

1.How can I place an order for SI5380A-D08067-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5380A-D08067-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5380A-D08067-GM reliable?

The price and inventory of SI5380A-D08067-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5380A-D08067-GM is usually 5 days.

3.What payment methods are accepted for SI5380A-D08067-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5380A-D08067-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5380A-D08067-GM?

SI5380A-D08067-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5380A-D08067-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5380A-D08067-GM?

For technical support, including SI5380A-D08067-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5380A-D08067-GM requirements.

6.How does Aetrix verify that SI5380A-D08067-GM is sourced from the original manufacturer or authorized distributors?

All SI5380A-D08067-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5380A-D08067-GM meets industry standards.

7.What is the process for return or replacement of SI5380A-D08067-GM?

All SI5380A-D08067-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5380A-D08067-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5380A-D08067-GM part is unused and in its original packaging.

Return procedure for SI5380A-D08067-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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