Skyworks Solutions Inc. SI5380A-D08236-GM

Overview

SI5380A-D08236-GM from Skyworks Solutions is a 12-output, integer-based JESD204B jitter attenuator and clock multiplexer optimized for wireless infrastructure. It delivers ultra-low phase noise (–159 dBc/Hz floor), 65 fs RMS jitter (12 kHz–20 MHz), and supports DCLK/SYSREF generation for Subclass 0 and 1. Its DSPLL architecture eliminates external VCXO and analog loop filters, enabling robust clock synthesis in remote radio units and small cells.

For engineers reviewing the SI5380A-D08236-GM datasheet, SI5380A-D08236-GM pinout, SI5380A-D08236-GM application, or SI5380A-D08236-GM equivalent, key selection criteria include JESD204B SYSREF phase matching capability, hitless input switching between LTE baseband clocks, holdover stability during RRU link loss, and 64-QFN package compatibility with high-density RF board layouts.

Technical Context

The SI5380A-D08236-GM implements Skyworks' 4th-generation DSPLL with a 15 GHz VCO, programmable digital loop filter (0.1 Hz–100 Hz bandwidth), and integrated 54 MHz crystal oscillator. It supports automatic freerun/lock/holdover mode transitions and stores up to 120 seconds of historical frequency data for holdover averaging.

Its architecture enables JESD204B-compliant clocking via dedicated DCLK and SYSREF outputs derived from the same Multisynth, ensuring phase-matched timing for ADC/DAC sampling in wireless transceivers. Input qualification includes LOS, OOF, and LOL detection with interrupt-driven status monitoring over I²C or SPI.

Key Specifications

Pinout & Package

SI5380A-D08236-GM is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev D datasheet Section 9 (Pin Description).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Compared with SI5380A-D08236-GM, Si5386A-D09286-GM extends JESD204B flexibility with phase tuning but increases complexity and cost, while LTC6957IUF-3#PBF offers lower integration and reduced holdover resilience-making SI5380A-D08236-GM optimal for GPS-disciplined RRU deployments requiring guaranteed jitter and holdover performance.

Availability

SI5380A-D08236-GM is available at Aetrix Electronics and suitable for remote radio units, small cell base stations, and JESD204B data converter systems requiring stable component supply across extended product lifecycles.

Supply support for SI5380A-D08236-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a U.S.-based semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless infrastructure, automotive, and IoT markets.

The SI5380 family was designed specifically for high-reliability wireless base station timing, integrating jitter attenuation, frequency synthesis, and holdover resilience into a single IC to replace multi-component clock trees in RAN equipment.

FAQ

What is the primary function of the SI5380A-D08236-GM in wireless infrastructure systems?

The SI5380A-D08236-GM serves as a jitter-attenuating clock multiplexer and synthesizer for wireless base stations. It generates ultra-low-jitter, phase-aligned clock signals-including JESD204B DCLK and SYSREF-for ADCs, DACs, and FPGAs in RRUs and small cells. Its DSPLL architecture replaces discrete VCXOs and loop filters, delivering 65 fs RMS jitter and robust holdover during GPS or fronthaul outages. SI5380A-D08236-GM is engineered to meet stringent 3GPP timing requirements in LTE and 5G NR deployments.

Does the SI5380A-D08236-GM support JESD204B Subclass 1 with phase-adjustable SYSREF?

No, the SI5380A-D08236-GM supports JESD204B Subclass 0 and Subclass 1 only for phase-matched DCLK/SYSREF pairs generated from the same Multisynth. It does not provide programmable phase offset between DCLK and SYSREF. For applications requiring dynamic SYSREF phase adjustment-such as beamformer calibration-the SI5386A-D09286-GM is the designated alternative. SI5380A-D08236-GM's fixed-phase relationship ensures deterministic latency but lacks runtime phase tuning capability.

What crystal frequency and specifications are required for the SI5380A-D08236-GM XA/XB interface?

The SI5380A-D08236-GM requires a 54 MHz fundamental-mode crystal connected to XA/XB pins. Skyworks specifies ±100 ppm total accuracy (including initial tolerance, temperature, voltage, load, and aging effects) for optimal holdover and freerun performance. The device integrates internal 8 pF load capacitors, eliminating external CL components. Crystal drive level must be ≤100 µW, and ESR should be ≤40 Ω. SI5380A-D08236-GM's oscillator circuit is optimized for this frequency to achieve its –159 dBc/Hz phase noise floor and 65 fs jitter specification.

How does the SI5380A-D08236-GM handle input clock failure in a remote radio unit?

Upon input clock failure, the SI5380A-D08236-GM automatically enters holdover mode using averaged historical frequency data stored over up to 120 seconds. It calculates a final holdover frequency from a programmable window within that history, minimizing phase disturbance. Output frequency drift during holdover depends solely on the 54 MHz crystal's stability. SI5380A-D08236-GM maintains <±0.2 ppm accuracy for >45 seconds-sufficient to sustain CPRI/eCPRI links until backup timing (e.g., IEEE 1588 PTP recovery) engages. Status flags (LOLb, INTRb) signal the transition for system-level response.

Is the SI5380A-D08236-GM pin-compatible with other Si5380 variants such as the Si5380A-D-GM?

Yes, all Si5380A-Dxxx-GM variants-including SI5380A-D08236-GM-share identical 64-QFN packaging, pinout, and electrical interface. Differences lie solely in factory-programmed configuration stored in OTP memory (e.g., output frequencies, input priorities, loop bandwidth). Hardware design, PCB layout, and power delivery are fully interchangeable. SI5380A-D08236-GM can be substituted for Si5380A-D-GM without board changes, provided the target application aligns with its preprogrammed settings for LTE/JESD204B use cases.