Skyworks Solutions Inc. SI5380A-D08751-GM

Overview

SI5380A-D08751-GM from Skyworks Solutions is a 12-output, integer-based JESD204B jitter attenuator and clock multiplexer optimized for wireless infrastructure. It delivers ultra-low phase noise (–159 dBc/Hz floor), 65 fs RMS jitter (12 kHz–20 MHz), and supports DCLK/SYSREF generation for Subclass 0 and 1 applications. Its DSPLL architecture eliminates external VCXO and analog loop filters, operating across –40 to +85 °C in a 64-QFN 9×9 mm package.

For engineers reviewing the SI5380A-D08751-GM datasheet, SI5380A-D08751-GM pinout, SI5380A-D08751-GM application, or SI5380A-D08751-GM equivalent, key selection considerations include JESD204B SYSREF phase-matching capability, hitless/ramped input switching behavior, holdover frequency averaging window configuration, and DSPLL loop bandwidth programmability (0.1 Hz–100 Hz).

Technical Context

The SI5380A-D08751-GM implements Skyworks' 4th-generation DSPLL with a 15 GHz VCO, digital loop filter, and configurable N/R dividers enabling up to 10 integer-related output frequencies. It supports automatic free-run, lock acquisition, locked, and holdover modes - with holdover frequency calculated from a programmable 120-second history window and user-defined averaging delay.

Input switching includes hitless (for phase-locked inputs), ramped (for plesiochronous inputs), and glitchless options. The device accepts four differential or LVCMOS inputs (11.52 MHz–737.28 MHz / 11.52 MHz–245.76 MHz), generates 12 outputs (480 kHz–1.47456 GHz differential / 480 kHz–245.76 MHz LVCMOS), and features I²C/SPI control with on-chip OTP memory.

Key Specifications

Pinout & Package

SI5380A-D08751-GM is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev D datasheet Section 9 (Pin Description) and validated against official package outline (Section 10).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Compared with SI5380A-D08751-GM, the Si5386A-D08752-GM adds phase-adjustable SYSREF and two more outputs but increases complexity and cost; the LTC6957IUF-3#PBF offers lower integration and no holdover, making it unsuitable for wireless infrastructure with uptime requirements.

Availability

SI5380A-D08751-GM is available at Aetrix Electronics and suitable for remote radio units, small cell base stations, and wireless backhaul terminals requiring stable component supply and long-term lifecycle support.

Supply support for SI5380A-D08751-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The SI5380 product line was designed specifically for ultra-low-jitter clock generation in wireless infrastructure - targeting JESD204B compliance, multi-input redundancy, and holdover resilience in RRU, RRH, and small cell applications.

FAQ

What is the primary function of the SI5380A-D08751-GM in wireless infrastructure systems?

The SI5380A-D08751-GM serves as a 12-output jitter attenuator and clock multiplexer optimized for JESD204B-compliant wireless base stations. It synthesizes ultra-low-jitter clocks (65 fs RMS) for ADC/DAC sampling, provides deterministic SYSREF generation, and supports hitless input switching and programmable holdover - all critical for RRU, small cell, and massive MIMO timing integrity. Its DSPLL architecture eliminates external VCXO and loop filter components.

Does the SI5380A-D08751-GM support JESD204B Subclass 1 with phase-adjustable SYSREF?

No. The SI5380A-D08751-GM supports JESD204B Subclass 0 and Subclass 1 DCLK/SYSREF generation only when phase-matched pairs are required from the same Multisynth. For full SYSREF phase adjustment capability, Skyworks recommends the SI5386A-D08752-GM. This limitation is explicitly documented in the Si5380 Rev D datasheet Section 3.1.2.

What crystal frequency and specifications are required for the XA/XB pins of the SI5380A-D08751-GM?

The SI5380A-D08751-GM requires a 54 MHz fundamental-mode crystal connected to XA/XB, with total accuracy of ±100 ppm (including initial tolerance, temperature, voltage, load, and aging). Internal 8 pF load capacitors eliminate external capacitors. The crystal must meet drive level ≤100 µW and ESR ≤40 Ω, per Table 5.12 in the Rev D datasheet. Using an external XO instead is possible but degrades output jitter performance.

How does the SI5380A-D08751-GM handle clock input failure in a redundant system?

Upon input failure, the SI5380A-D08751-GM automatically enters holdover mode using an averaged historical frequency derived from up to 120 seconds of prior locked operation. The averaging window size and delay before failure are programmable to minimize phase disturbance. When a valid input returns, it supports ramped exit (linear frequency transition) at user-selectable rates (0.2–40,000 ppm/s) to prevent DAC/ADC glitches - a feature confirmed in Section 3.1.10 of the datasheet.

Is the SI5380A-D08751-GM pin-compatible with other Si5380 variants such as the SI5380A-D-GM?

Yes. All Si5380A-Dxxx-GM variants share identical 64-QFN 9×9 mm packaging, pinout, and electrical interface. The "D08751" suffix denotes a factory-preprogrammed configuration (e.g., specific JESD204B output frequencies and input priorities), but mechanical and functional pin compatibility is maintained across the Si5380A-D-GM family per Skyworks' Ordering Guide (Table 2.1) and Package Outline (Section 10).