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Skyworks Solutions Inc. SI5391B-A15691-GMR
- Part No.:
- SI5391B-A15691-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- 64-VFQFN Exposed Pad
- Datasheet:
-
SI5391B-A15691-GMR.pdf
- Description:
- ULTRA LOW-JITTER, 12-OUTPUT, ANY
- Quantity:
- Payment:
- Shipping:
Inventory:1,635
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Product details
Overview
SI5391B-A15691-GMR from Skyworks Solutions is a 12-output, ultra-low-jitter clock generator supporting any-frequency synthesis up to 350 MHz per output, with 75 fs RMS phase jitter in integer mode and 115 fs RMS in fractional mode. It features 4 inputs (XA/XB crystal or IN0–IN2 clocks), programmable LVDS/LVPECL/LVCMOS/CML/HCSL outputs, and operates across –40°C to +85°C in a 64-QFN 9×9 mm package - designed for 100G/200G/400G switch clock trees and FPGA timing.
For engineers reviewing the SI5391B-A15691-GMR datasheet, SI5391B-A15691-GMR pinout, SI5391B-A15691-GMR application, or SI5391B-A15691-GMR equivalent, key selection criteria include its Grade B 350 MHz output limit, Precision Calibration compatibility (as indicated by "A15691" suffix), zero-delay mode support, I²C/SPI configurability, and factory-programmable OTP memory for production-ready timing solutions.
Technical Context
The SI5391B-A15691-GMR integrates a wide-band PLL with proprietary MultiSynth™ fractional synthesizers to generate independent, glitch-free frequencies on all 12 differential outputs. Its architecture supports both integer and fractional synthesis modes, enabling precise frequency plans from 100 Hz to 350 MHz per output while maintaining sub-100 fs jitter performance optimized for high-speed SerDes.
Input flexibility includes external crystal (25–54 MHz on XA/XB) or differential/LVCMOS clocks (10–750 MHz / 10–250 MHz), with automatic input selection via IN_SEL pins or register control. Output drivers are independently configurable for format (LVDS, LVPECL, CML, HCSL, LVCMOS), voltage (1.8 V/2.5 V/3.3 V), common-mode level, and termination - enabling full clock-tree consolidation on a single IC.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count | 12 fully independent differential outputs, each configurable as LVDS/LVPECL/CML/HCSL or LVCMOS |
| Max output frequency | 350 MHz - defines Grade B's upper limit for stable, low-jitter operation (vs. Grade A's 1028 MHz) |
| Phase jitter (RMS) | 75 fs (integer mode), 115 fs (fractional mode) - critical for 56G/112G PAM4 SerDes reference stability |
| Input support | Crystal (25–54 MHz on XA/XB) or differential clock (10–750 MHz) or LVCMOS clock (10–250 MHz) |
| Supply voltages | VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%; independent VDDO pins per output (1.8/2.5/3.3 V) |
| Package & temp | 64-QFN 9×9 mm, –40°C to +85°C - industrial-grade thermal and mechanical compatibility |
| Configuration interface | I²C or SPI serial interface with in-circuit programmable OTP NVM - enables field reconfiguration and factory pre-programming |
Pinout & Package
SI5391B-A15691-GMR uses a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks' official Si5391 pinout documentation (Rev. 0.7, Section 9).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| XA, XB | Crytal oscillator input | Accepts 25–54 MHz fundamental-mode crystal; internal load caps disabled when used as differential clock input |
| IN0, IN1, IN2 | Secondary clock inputs | Differential or LVCMOS-compatible inputs (10–750 MHz / 10–250 MHz); selectable via IN_SEL[1:0] pins or register |
| OUT0–OUT11 | Differential clock outputs | 12 individually configurable outputs; each supports LVDS/LVPECL/CML/HCSL or LVCMOS with programmable swing and VCM |
| FB_IN, FB_INb | External feedback input | Required for zero-delay mode; accepts ac-coupled differential feedback from any output (e.g., OUT9A) |
| OEb | Global output enable | Active-low pin disabling all outputs simultaneously; individual outputs can be disabled via register control |
| INTRb | Interrupt output | Open-drain status flag indicating LOS/LOL events; maskable via register configuration |
| SCL, SDA, CSb, SCLK, SDIO | I²C/SPI interface | Supports dual serial protocols; allows in-system programming and real-time DCO adjustment |
Key Features
| Feature | Design Value |
|---|---|
| Any-frequency synthesis | Generates arbitrary output frequencies (100 Hz–350 MHz) from any valid input - eliminates need for multiple oscillators/buffers |
| Zero-delay mode | Enables fixed, minimized input-to-output latency by closing PLL feedback externally - essential for deterministic timing paths |
| Glitchless DCO mode | Supports real-time frequency tuning (down to 0.001 ppb steps) without output glitches - ideal for margining and FIFO rate control |
| Multi-format outputs | Each of 12 outputs independently set to LVDS, LVPECL, CML, HCSL, or LVCMOS with programmable amplitude and common-mode voltage |
| Precision Calibration support | "A15691" suffix confirms factory calibration for enhanced jitter linearity - validated for 156.25/312.5 MHz domains per Grade P spec |
Applications
| 100G/400G Ethernet Switches | FPGA & ASIC Clock Tree Consolidation |
|---|---|
Use Scenario: High-density data center switches requiring synchronized 100G/400G SerDes lanes with strict jitter budgets. IC Role / Device Role / Timing Role: Primary clock generator delivering 156.25 MHz, 312.5 MHz, and 625 MHz reference clocks to multiple SerDes blocks. Use Value: Sub-100 fs RMS jitter ensures compliance with IEEE 802.3bs and OIF CEI-112G-LR jitter masks at PAM4 signaling rates. |
Use Scenario: Multi-core SoC/FPGA platforms needing diverse clock domains (processor, DDR, PCIe, transceivers). IC Role / Device Role / Timing Role: Single-chip clock tree replacing discrete XO + buffer + level-shifter combinations across voltage islands. Use Value: Independent VDDO pins and format configurability eliminate interposer-level signal translation and reduce board area by >40%. |
| 56G/112G PAM4 Reference Timing | OTN & Metro Transport Equipment |
Use Scenario: Coherent optical modules and DSP-based line cards demanding ultra-stable 156.25/312.5 MHz references. IC Role / Device Role / Timing Role: Precision-calibrated clock source operating in Grade B with A15691 configuration for optimized PAM4 SerDes locking. Use Value: Factory-trimmed linearity enables 95 fs MAX RMS jitter at 156.25 MHz - meeting ITU-T G.709.1 and OTUCn jitter tolerance. |
Use Scenario: OTN framers/mappers requiring synchronous clocking across multiple line/mapping layers (ODU0–ODU4). IC Role / Device Role / Timing Role: Centralized timing hub generating 25/50/100/125/200 MHz clocks with holdover and hitless switching capability. Use Value: Input failover and status monitoring (LOS/LOL) via INTRb ensure carrier-grade timing continuity during reference loss events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SI5391A-A15691-GMR | Higher 1028 MHz max output frequency; same pinout, package, and calibration ID (A15691) | Required for designs needing >350 MHz outputs (e.g., 625 MHz SerDes, PCIe Gen6) | Select if frequency headroom beyond 350 MHz is needed; otherwise SI5391B-A15691-GMR offers cost-optimized performance. |
| SI5392B-A15691-GM | Lower power, 8-output variant with identical Grade B frequency range (≤350 MHz) and same A15691 calibration | Suitable for space-constrained or thermally sensitive applications where 12 outputs are unnecessary | Choose for reduced BOM count and lower thermal dissipation when 8 outputs suffice - retains full software compatibility with ClockBuilder Pro. |
Compared with SI5391A-A15691-GMR and SI5392B-A15691-GM, the SI5391B-A15691-GMR delivers optimal balance of output count (12), frequency capability (≤350 MHz), and Precision Calibration - making it the preferred choice for mid-range 100G–400G systems where cost, footprint, and jitter are co-optimized.
Availability
SI5391B-A15691-GMR is available at Aetrix Electronics and suitable for 100G/400G Ethernet switches, FPGA-based telecom infrastructure, and OTN transport equipment requiring stable component supply, long-term lifecycle assurance, and calibrated timing performance.
Supply support for SI5391B-A15691-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and precision clock innovation.
The SI5391 family was engineered to replace multi-component clock trees in high-speed networking and computing - delivering ultra-low jitter, software-defined flexibility, and single-chip consolidation for 100G+ systems.
FAQ
What does the "A15691" suffix in SI5391B-A15691-GMR indicate?
The "A15691" suffix identifies a factory-preprogrammed configuration with Precision Calibration applied to key frequency domains (156.25 MHz and 312.5 MHz), ensuring ≤95 fs RMS phase jitter performance. This calibration is performed during manufacturing and stored in the device's OTP memory - meaning SI5391B-A15691-GMR ships ready for 56G/112G PAM4 applications without user configuration.
Can SI5391B-A15691-GMR operate in zero-delay mode, and what is required?
Yes, SI5391B-A15691-GMR supports zero-delay mode for deterministic input-to-output latency. To enable it, configure the device via I²C/SPI to open the internal feedback loop and route one output (e.g., OUT9A) back to FB_IN/FB_INb pins using an ac-coupled differential path. External termination (100 Ω differential) and careful PCB layout per Skyworks' AN1109 are mandatory to achieve sub-100 ps delay consistency.
How many independent voltage supplies does SI5391B-A15691-GMR support for its outputs?
SI5391B-A15691-GMR provides 12 dedicated VDDO pins - one per output - allowing independent selection of 1.8 V, 2.5 V, or 3.3 V supply for each driver. This enables mixed-signal timing across voltage domains (e.g., 1.8 V FPGA core, 2.5 V DDR PHY, 3.3 V SerDes analog block) without external level shifters, directly supporting heterogeneous system-on-module designs.
Is SI5391B-A15691-GMR compatible with ClockBuilder Pro software?
Yes, SI5391B-A15691-GMR is fully supported by Skyworks' ClockBuilder Pro software. The tool validates frequency plans, generates register maps, exports .c files for embedded initialization, and enables field reprogramming via I²C/SPI. For the A15691 configuration, ClockBuilder Pro recognizes the preloaded calibration and restricts editable parameters to preserve jitter performance guarantees.
What is the maximum allowable input clock frequency on IN0–IN2 for SI5391B-A15691-GMR?
The maximum input clock frequency on IN0, IN1, or IN2 is 750 MHz for differential signals and 250 MHz for LVCMOS signals, as specified in the Si5391 datasheet (Rev. 0.7, Table 6.3). These limits apply regardless of the "A15691" calibration - the input stage design is identical across Grade A/B/C/D variants, and SI5391B-A15691-GMR inherits the full Grade B input specification.
SI5391B-A15691-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 64-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Type:
- Clock Generator
- PLL:
- Yes
- Input:
- Clock, Crystal, LVCMOS
- Output:
- CML, HCSL, LVCMOS, LVDS, LVPECL
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 4:12
- Differential - Input:Output:
- Yes/Yes
- Frequency - Max:
- 350MHz
- Divider/Multiplier:
- Yes/No
- Voltage - Supply:
- 1.71V ~ 1.89V, 3.14V ~ 3.47V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 64-QFN (9x9)
SI5391B-A15691-GMR FAQ
1.How can I place an order for SI5391B-A15691-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5391B-A15691-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5391B-A15691-GMR reliable?
The price and inventory of SI5391B-A15691-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5391B-A15691-GMR is usually 5 days.
3.What payment methods are accepted for SI5391B-A15691-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5391B-A15691-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5391B-A15691-GMR?
SI5391B-A15691-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5391B-A15691-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5391B-A15691-GMR?
For technical support, including SI5391B-A15691-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5391B-A15691-GMR requirements.
6.How does Aetrix verify that SI5391B-A15691-GMR is sourced from the original manufacturer or authorized distributors?
All SI5391B-A15691-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5391B-A15691-GMR meets industry standards.
7.What is the process for return or replacement of SI5391B-A15691-GMR?
All SI5391B-A15691-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5391B-A15691-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5391B-A15691-GMR part is unused and in its original packaging.
Return procedure for SI5391B-A15691-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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