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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5392J-A-GM

Name: SI5392J-A-GM
Brand: Skyworks Solutions Inc.
SKU: SI5392J-A-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5392J-A-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5392J-A-GM.pdf

Description:: SINGLE PLL JITTER ATTENUATOR WIT

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5392J-A-GM from Skyworks Solutions is a 4-input, 2-output any-frequency jitter attenuator/clock multiplier with integrated crystal reference, delivering 85 fs RMS phase jitter in integer mode and supporting output frequencies from 100 Hz to 1028 MHz. It operates in free-run, locked, and holdover modes and is used in 100G/400G networking line cards requiring ultra-low-jitter clock synthesis with board-space-saving integration.

For engineers reviewing the SI5392J-A-GM datasheet, SI5392J-A-GM pinout, SI5392J-A-GM application, or SI5392J-A-GM equivalent, key selection criteria include its internal reference architecture, 44-LGA 7×7 mm package, dual-output programmability via I²C/SPI, and compliance with ITU-T G.8262 SyncE EEC Options 1 and 2.

Technical Context

The SI5392J-A-GM implements a fourth-generation DSPLL® with MultiSynth™ technology, using an integrated crystal oscillator (OSC) as its reference source-eliminating external XTAL components and reducing acoustic noise sensitivity during thermal ramps. Its fractional input dividers (P) enable hitless switching between fractionally related input clocks (e.g., 8 kHz–750 MHz differential), while independent MultiSynth dividers (N) generate integer or fractional output frequencies per channel.

It supports dynamic phase adjustment, programmable DSPLL loop bandwidth (0.1 Hz–4 kHz for Grades A/B/C/D; fixed 100 Hz for P/E), and DCO mode with 0.001 ppb step size. The device features status monitoring (LOS/OOF/LOL), zero-delay mode (with IN3 repurposed as FB_IN), and ramped holdover exit using user-selectable slew rates (0.2–40,000 ppm/s).

Key Specifications

Parameter	Value and Actual Design Meaning
Input Count / Output Count	4 differential/LVCMOS inputs, 2 programmable outputs - enables redundancy and multi-domain clock distribution in compact systems.
Phase Jitter (RMS)	85 fs (integer mode), 100 fs (fractional mode) - meets stringent 56G/112G PAM4 SerDes timing budgets without external cleanup.
Output Frequency Range	100 Hz–1028 MHz (differential), 100 Hz–250 MHz (LVCMOS) - covers Ethernet, OTN, and test equipment clocking requirements.
Reference Type	Integrated crystal oscillator - eliminates external XTAL, reduces BOM count, improves reliability, and suppresses acoustic noise coupling.
Compliance	ITU-T G.8262 (SyncE EEC Options 1 & 2), G.8262.1 (eEEC) - certified for carrier-grade synchronous Ethernet applications.
Supply Voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5% - supports low-power digital core and high-fidelity analog clock path separation.
Operating Temp	–40 °C to +85 °C - qualified for industrial and telecom infrastructure environments.

Pinout & Package

SI5392J-A-GM is housed in a 44-pin LGA (Land Grid Array) package, 7 mm × 7 mm, 0.5 mm pitch, with exposed thermal pad. This surface-mount package provides superior thermal performance and signal integrity for high-frequency clock distribution.

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential/LVCMOS clock inputs	Supports automatic/manual selection of up to four reference sources; IN3 becomes FB_IN in zero-delay mode.
OUT0, OUT1	Differential or LVCMOS clock outputs	Individually configurable for LVDS/LVPECL/CML/HCSL/LVCMOS; each with independent amplitude and format control.
XA/XB	Crystal oscillator terminals	Internally connected to integrated resonator - no external crystal or load capacitors required.
SCL/SDA	I²C serial interface	Enables in-system configuration and status readback without requiring SPI hardware.
RSTb	Active-low reset input	Triggers hard reset: reloads NVM configuration and reinitializes all PLL blocks and outputs.
LOL	Loss-of-lock indicator	Open-drain output signals loss of phase lock to selected input - critical for system fault detection and failover logic.

Key Features

Feature	Design Value
Integrated crystal reference	Eliminates external XTAL, saves ~3 mm² PCB area, removes crystal layout sensitivity, and improves long-term aging stability.
Enhanced hitless switching	Minimizes output phase transients to ≤0.2 ns typical during input clock switchover - essential for hitless network synchronization.
Programmable holdover window	Stores up to 120 s of historical frequency data and calculates averaged holdover frequency from a programmable time window - reduces phase jump on input failure.
Frequency-on-the-fly (FOTF)	Allows real-time, independent frequency updates on one MultiSynth without disrupting other outputs - enables dynamic rate adaptation in test equipment.
In-circuit NVM programming	Retains full configuration across power cycles - ensures deterministic startup behavior and eliminates boot-time configuration overhead.

Applications

100G/400G Networking Line Cards	Synchronous Ethernet (SyncE)
Use Scenario: High-density line cards in optical transport platforms require precise, low-jitter clocks for multiple SerDes lanes and packet processing ASICs. IC Role / Device Role / Timing Role: Jitter attenuator and clock multiplier generating synchronized 156.25 MHz, 312.5 MHz, and 625 MHz clocks from OC-192 or 100GE reference inputs. Use Value: 85 fs RMS jitter ensures <1e-12 BER in 112G PAM4 links; integrated reference simplifies layout and improves thermal stability over temperature ramps.	Use Scenario: Carrier-grade Ethernet switches implementing ITU-T G.8262-compliant timing distribution across metro networks. IC Role / Device Role / Timing Role: Primary timing IC providing EEC Option 1/2 compliant clocks to PHYs and MACs, with holdover support during reference loss. Use Value: Programmable holdover averaging and ramped exit maintain phase continuity during >120 s reference outages - meeting G.8262 wander limits.
OTN Muxponders	Medical Imaging Systems
Use Scenario: Aggregating multiple client-side OTN signals (e.g., ODU0–ODU4) into a single line-side wavelength with strict jitter accumulation limits. IC Role / Device Role / Timing Role: Jitter cleaner and frequency translator converting asynchronous client clocks to line-rate synchronous clocks (e.g., 10.709 GHz, 43.018 GHz). Use Value: 100 fs fractional-mode jitter meets ITU-T G.709 OPUk/ODUk jitter masks; DSPLL loop bandwidth programmability allows tailoring attenuation to specific input noise profiles.	Use Scenario: MRI and PET scanner timing subsystems requiring ultra-stable, low-phase-noise clocks for ADC sampling and RF excitation control. IC Role / Device Role / Timing Role: Master clock generator producing synchronized 125 MHz, 250 MHz, and 1 GHz clocks for digitizers, gradient drivers, and RF synthesizers. Use Value: Integrated crystal reference avoids microphonic noise from external crystals near magnetic fields; 69–85 fs jitter enables sub-picosecond time-of-flight resolution.

100G/400G Networking Line Cards

Synchronous Ethernet (SyncE)

Use Scenario: High-density line cards in optical transport platforms require precise, low-jitter clocks for multiple SerDes lanes and packet processing ASICs.

IC Role / Device Role / Timing Role: Jitter attenuator and clock multiplier generating synchronized 156.25 MHz, 312.5 MHz, and 625 MHz clocks from OC-192 or 100GE reference inputs.

Use Value: 85 fs RMS jitter ensures <1e-12 BER in 112G PAM4 links; integrated reference simplifies layout and improves thermal stability over temperature ramps.

Use Scenario: Carrier-grade Ethernet switches implementing ITU-T G.8262-compliant timing distribution across metro networks.

IC Role / Device Role / Timing Role: Primary timing IC providing EEC Option 1/2 compliant clocks to PHYs and MACs, with holdover support during reference loss.

Use Value: Programmable holdover averaging and ramped exit maintain phase continuity during >120 s reference outages - meeting G.8262 wander limits.

OTN Muxponders

Medical Imaging Systems

Use Scenario: Aggregating multiple client-side OTN signals (e.g., ODU0–ODU4) into a single line-side wavelength with strict jitter accumulation limits.

IC Role / Device Role / Timing Role: Jitter cleaner and frequency translator converting asynchronous client clocks to line-rate synchronous clocks (e.g., 10.709 GHz, 43.018 GHz).

Use Value: 100 fs fractional-mode jitter meets ITU-T G.709 OPUk/ODUk jitter masks; DSPLL loop bandwidth programmability allows tailoring attenuation to specific input noise profiles.

Use Scenario: MRI and PET scanner timing subsystems requiring ultra-stable, low-phase-noise clocks for ADC sampling and RF excitation control.

IC Role / Device Role / Timing Role: Master clock generator producing synchronized 125 MHz, 250 MHz, and 1 GHz clocks for digitizers, gradient drivers, and RF synthesizers.

Use Value: Integrated crystal reference avoids microphonic noise from external crystals near magnetic fields; 69–85 fs jitter enables sub-picosecond time-of-flight resolution.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SI5392C-A-GM	External crystal reference (44-QFN), integer-only synthesis, same 4-in/2-out topology	Requires external 48–54 MHz XTAL; better suited for cost-sensitive designs where board space is less constrained	Select when external crystal layout is acceptable and fractional synthesis is unnecessary.
SI5392J-B-GM	Same integrated reference, but limited to 350 MHz max output frequency and reduced jitter spec (not specified in datasheet)	Targeted at lower-speed applications like 10G/40G Ethernet or legacy SONET where >350 MHz outputs are unused	Choose for legacy infrastructure upgrades where full 1028 MHz range is not required.

Compared with SI5392C-A-GM and SI5392J-B-GM, the SI5392J-A-GM uniquely combines integrated reference, full 1028 MHz output capability, and integer/fractional synthesis-making it optimal for next-gen 400G+ systems where board area, jitter margin, and frequency flexibility are simultaneously critical.

Availability

SI5392J-A-GM is available at Aetrix Electronics and suitable for 100G/400G networking line cards, Synchronous Ethernet infrastructure, OTN muxponders, medical imaging timing subsystems, and test and measurement equipment requiring stable component supply and long-term lifecycle assurance.

Supply support for SI5392J-A-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and precision analog solutions for communications, automotive, and industrial markets.

The SI5392J-A-GM belongs to Skyworks' Si539x family of any-frequency jitter attenuators, designed specifically for high-speed networking and telecom infrastructure demanding ultra-low jitter, integrated references, and robust holdover performance.

FAQ

What is the reference architecture used in the SI5392J-A-GM?

The SI5392J-A-GM uses an integrated crystal oscillator (OSC) as its reference source-no external crystal or oscillator is required. This Grade J device embeds the resonator within the 44-LGA package, eliminating external load capacitors and reducing sensitivity to acoustic noise during thermal transients. The SI5392J-A-GM's internal reference directly feeds the DSPLL, enabling faster startup and improved long-term stability compared to external XTAL-based variants.

Does the SI5392J-A-GM support both integer and fractional frequency synthesis?

Yes, the SI5392J-A-GM supports both integer and fractional frequency synthesis modes, enabling generation of any output frequency from 100 Hz to 1028 MHz (differential) based on input frequencies from 8 kHz to 750 MHz. This flexibility allows the SI5392J-A-GM to replace multiple fixed-ratio clock generators in complex systems such as 400G line cards, where diverse SerDes lane rates (e.g., 10.3125 Gbps, 25.78125 Gbps, 53.125 Gbps) must be derived from common references.

How does the SI5392J-A-GM handle input clock failures?

Upon input clock failure, the SI5392J-A-GM automatically enters holdover mode using up to 120 seconds of stored historical frequency data to compute an averaged holdover frequency. The SI5392J-A-GM supports programmable holdover window size and delay to exclude corrupted pre-failure data, and offers ramped exit-linearly slewing output frequency back to target at rates from 0.2 to 40,000 ppm/s-to minimize phase discontinuity. This behavior is fully configurable via I²C/SPI.

What package type and footprint does the SI5392J-A-GM use?

The SI5392J-A-GM is packaged in a 44-pin Land Grid Array (LGA), 7 mm × 7 mm, 0.5 mm pitch, with an exposed thermal pad. Unlike QFN variants, this LGA package eliminates gull-wing leads, improving high-frequency signal integrity and thermal dissipation. The SI5392J-A-GM's footprint is identical to other Si5392J-x-GM variants and pin-compatible with Si5342J-A-GM for drop-in migration in existing designs.

Can the SI5392J-A-GM be configured without external programming hardware?

Yes, the SI5392J-A-GM includes in-circuit programmable non-volatile memory (NVM) and powers up with a known configuration. It supports I²C and SPI interfaces for field reconfiguration, and factory preprogrammed units are available. ClockBuilder Pro software from Skyworks enables intuitive GUI-based configuration of all parameters-including jitter attenuation bandwidth, output formats, and holdover settings-without requiring custom firmware or dedicated programmers. The SI5392J-A-GM retains its full configuration across power cycles.

SI5392J-A-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5392J-A-GM FAQ

1.How can I place an order for SI5392J-A-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5392J-A-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5392J-A-GM reliable?

The price and inventory of SI5392J-A-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5392J-A-GM is usually 5 days.

3.What payment methods are accepted for SI5392J-A-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5392J-A-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5392J-A-GM?

SI5392J-A-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5392J-A-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5392J-A-GM?

For technical support, including SI5392J-A-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5392J-A-GM requirements.

6.How does Aetrix verify that SI5392J-A-GM is sourced from the original manufacturer or authorized distributors?

All SI5392J-A-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5392J-A-GM meets industry standards.

7.What is the process for return or replacement of SI5392J-A-GM?

All SI5392J-A-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5392J-A-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5392J-A-GM part is unused and in its original packaging.

Return procedure for SI5392J-A-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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