Skyworks Solutions Inc. SI5394E-A-GMR

Overview

SI5394E-A-GMR from Skyworks Solutions is a 4-input, 4-output ultra-low-jitter clock multiplier and jitter attenuator with integrated crystal reference, delivering 71 fs RMS phase jitter (Grade E), programmable DSPLL loop bandwidth (fixed at 100 Hz for Grade E), and support for hitless switching in 56G PAM4 SerDes clocking applications.

For engineers reviewing the SI5394E-A-GMR datasheet, SI5394E-A-GMR pinout, SI5394E-A-GMR application, or SI5394E-A-GMR equivalent, this device serves as a precision timing solution requiring deterministic jitter performance, holdover stability with integrated reference, and multi-domain frequency synthesis for high-speed networking line cards and SyncE-compliant systems.

Technical Context

The SI5394E-A-GMR implements fourth-generation DSPLL® architecture with Multi-Synth™ dividers to perform jitter attenuation and any-frequency multiplication. Its integrated crystal oscillator eliminates external XTAL components and reduces acoustic noise sensitivity during thermal ramping.

It supports free-run, locked, and holdover modes with programmable 120-second frequency history averaging for holdover, and enables frequency-on-the-fly updates per MultiSynth without disturbing other outputs - all configured via I²C/SPI with on-chip NVM for known-power-up state.

Key Specifications

Pinout & Package

SI5394E-A-GMR is housed in a 44-pin LGA package (7 × 7 mm), compatible with standard reflow profiles and offering improved thermal performance over QFN equivalents. Pin assignments follow Skyworks' standardized Si539x pinout for Grades J/K/L/M/E.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Compared with SI5394J-A-GMR, SI5394E-A-GMR trades broader synthesis flexibility for tighter holdover calibration and enhanced acoustic robustness; versus SI5344D-A-GMR, it delivers 64 fs lower jitter and eliminates crystal-related layout sensitivity - critical for dense, thermally cycled telecom modules.

Availability

SI5394E-A-GMR is available at Aetrix Electronics and suitable for 56G SerDes clocking, OTN transponder timing, and Synchronous Ethernet line cards requiring stable component supply, long-term lifecycle assurance, and RoHS-6 compliance.

Supply support for SI5394E-A-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clocking innovation.

The Si539x family was designed specifically for high-performance networking and datacenter timing, addressing jitter, holdover stability, and multi-domain synchronization challenges in 56G+ SerDes and ITU-T-compliant systems.

FAQ

What is the phase jitter specification for SI5394E-A-GMR, and under what conditions is it measured?

The SI5394E-A-GMR delivers 71 fs RMS phase jitter (12 kHz–20 MHz integration band), measured per IEEE 1149.1 and ITU-T G.8262 Annex I using a 100 MHz differential output clock, 100 Hz DSPLL loop bandwidth, and integrated crystal reference. This value applies to Grade E devices operating within –40°C to +85°C ambient temperature and specified supply voltage ranges.

Does SI5394E-A-GMR require an external crystal, and what happens if one is connected?

No, SI5394E-A-GMR uses an integrated crystal reference and does not require or support external crystals. Connecting an external crystal or oscillator to XA/XB pins on SI5394E-A-GMR is prohibited and may cause internal circuit damage, as confirmed in Skyworks' Final Data Sheet Section 4.6 and Figure 5 notes.

How many independent frequency domains does SI5394E-A-GMR support, and what defines a domain?

SI5394E-A-GMR supports up to two independent frequency domains, as defined in Section 4.9.2 of the Skyworks datasheet. Each domain comprises one or more outputs sharing the same DSPLL and MultiSynth configuration - enabling simultaneous generation of unrelated frequencies (e.g., 156.25 MHz for Ethernet and 297 MHz for video) with isolated jitter transfer paths.

Can SI5394E-A-GMR operate in zero-delay mode, and how does it affect pin functionality?

Yes, SI5394E-A-GMR supports zero-delay mode, which repurposes IN3 as feedback input (FB_IN). In this mode, IN3 is no longer available as a selectable clock input, and manual selection via CLKIN_SEL[1:0] is restricted to IN0–IN2. Zero-delay mode requires specific register configuration and is intended for applications requiring minimal propagation delay between input and output clocks.

What serial interfaces does SI5394E-A-GMR support, and are both available simultaneously?

SI5394E-A-GMR supports I²C and SPI serial interfaces, but only one can be active at a time. Interface selection is determined by strap pin configuration at power-up: I²C is enabled when SDO is pulled high, SPI when SDO is pulled low. Both interfaces provide full access to registers, NVM programming, and status monitoring per the Si5395-94-92 Family Reference Manual.